34 lines
675 B
C
34 lines
675 B
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2020 Linumiz
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* Author: Saravanan Sekar <saravanan@linumiz.com>
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*/
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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void z_arm_platform_init(void)
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{
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SYS_UnlockReg();
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/* system clock init */
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SystemInit();
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/* Enable HXT clock (external XTAL 12MHz) */
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CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
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/* Wait for HXT clock ready */
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CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
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/* Set core clock as PLL_FOUT source */
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CLK_SetCoreClock(FREQ_192MHZ);
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/* Set both PCLK0 and PCLK1 as HCLK/2 */
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CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2);
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SystemCoreClockUpdate();
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SYS_LockReg();
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}
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