87 lines
2.6 KiB
C
87 lines
2.6 KiB
C
/*
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* Copyright (c) 2023 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control/clock_control_numaker.h>
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/* Hardware and starter kit includes. */
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#include <NuMicro.h>
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void z_arm_platform_init(void)
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{
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SystemInit();
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/* Unlock protected registers */
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SYS_UnlockReg();
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/*
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* -------------------
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* Init System Clock
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* -------------------
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*/
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt)
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/* Enable/disable 4~24 MHz external crystal oscillator (HXT) */
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if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) {
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CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
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/* Wait for HXT clock ready */
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CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
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} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) {
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CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
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}
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt)
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/* Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT) */
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if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) {
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CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
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/* Wait for LXT clock ready */
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CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
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} else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) {
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CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
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}
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#endif
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/* Enable 12 MHz high-speed internal RC oscillator (HIRC) */
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CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
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/* Wait for HIRC clock ready */
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CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
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/* Enable 10 KHz low-speed internal RC oscillator (LIRC) */
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CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
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/* Wait for LIRC clock ready */
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CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48)
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/* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48) */
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if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_ENABLE) {
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CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
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/* Wait for HIRC48 clock ready */
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CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
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} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_DISABLE) {
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CLK_DisableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
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}
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv)
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/* Set CLK_PCLKDIV register on request */
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CLK->PCLKDIV = DT_PROP(DT_NODELABEL(scc), clk_pclkdiv);
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock)
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/* Set core clock (HCLK) on request */
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CLK_SetCoreClock(DT_PROP(DT_NODELABEL(scc), core_clock));
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#endif
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/*
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* Update System Core Clock
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* User can use SystemCoreClockUpdate() to calculate SystemCoreClock.
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*/
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SystemCoreClockUpdate();
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/* Lock protected registers */
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SYS_LockReg();
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}
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