117 lines
3.4 KiB
C
117 lines
3.4 KiB
C
/*
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* Copyright (c) 2024 Nordic Semiconductor ASA.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/cache.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <hal/nrf_hsfll.h>
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#include <hal/nrf_lrcconf.h>
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#include <hal/nrf_spu.h>
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#include <soc/nrfx_coredep.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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#if defined(NRF_APPLICATION)
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#define HSFLL_NODE DT_NODELABEL(cpuapp_hsfll)
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#elif defined(NRF_RADIOCORE)
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#define HSFLL_NODE DT_NODELABEL(cpurad_hsfll)
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#endif
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#define FICR_ADDR_GET(node_id, name) \
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DT_REG_ADDR(DT_PHANDLE_BY_NAME(node_id, nordic_ficrs, name)) + \
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DT_PHA_BY_NAME(node_id, nordic_ficrs, name, offset)
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#define SPU_INSTANCE_GET(p_addr) \
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((NRF_SPU_Type *)((p_addr) & (ADDRESS_REGION_Msk | \
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ADDRESS_SECURITY_Msk | \
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ADDRESS_DOMAIN_Msk | \
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ADDRESS_BUS_Msk)))
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static void power_domain_init(void)
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{
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/*
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* Set:
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* - LRCCONF010.POWERON.MAIN: 1
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* - LRCCONF010.POWERON.ACT: 1
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* - LRCCONF010.RETAIN.MAIN: 1
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* - LRCCONF010.RETAIN.ACT: 1
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*
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* This is done here at boot so that when the idle routine will hit
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* WFI the power domain will be correctly retained.
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*/
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nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
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nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
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nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
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nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
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}
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static int trim_hsfll(void)
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{
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#if defined(HSFLL_NODE)
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NRF_HSFLL_Type *hsfll = (NRF_HSFLL_Type *)DT_REG_ADDR(HSFLL_NODE);
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nrf_hsfll_trim_t trim = {
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.vsup = sys_read32(FICR_ADDR_GET(HSFLL_NODE, vsup)),
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.coarse = sys_read32(FICR_ADDR_GET(HSFLL_NODE, coarse)),
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.fine = sys_read32(FICR_ADDR_GET(HSFLL_NODE, fine))
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};
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LOG_DBG("Trim: HSFLL VSUP: 0x%.8x", trim.vsup);
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LOG_DBG("Trim: HSFLL COARSE: 0x%.8x", trim.coarse);
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LOG_DBG("Trim: HSFLL FINE: 0x%.8x", trim.fine);
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nrf_hsfll_clkctrl_mult_set(hsfll,
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DT_PROP(HSFLL_NODE, clock_frequency) /
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DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency));
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nrf_hsfll_trim_set(hsfll, &trim);
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nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
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/* HSFLL task frequency change needs to be triggered twice to take effect.*/
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nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
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LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP);
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LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE);
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LOG_DBG("NRF_HSFLL->TRIM.FINE = %d", hsfll->TRIM.FINE);
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#endif /* defined(HSFLL_NODE) */
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return 0;
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}
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static int nordicsemi_nrf54h_init(void)
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{
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sys_cache_instr_enable();
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sys_cache_data_enable();
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power_domain_init();
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trim_hsfll();
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ccm030), okay)
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/* DMASEC is set to non-secure by default, which prevents CCM from
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* accessing secure memory. Change DMASEC to secure.
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*/
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uint32_t ccm030_addr = DT_REG_ADDR(DT_NODELABEL(ccm030));
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NRF_SPU_Type *spu = SPU_INSTANCE_GET(ccm030_addr);
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nrf_spu_periph_perm_dmasec_set(spu, nrf_address_slave_get(ccm030_addr), true);
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#endif
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return 0;
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}
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void arch_busy_wait(uint32_t time_us)
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{
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nrfx_coredep_delay_us(time_us);
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}
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SYS_INIT(nordicsemi_nrf54h_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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