212 lines
7.0 KiB
C
212 lines
7.0 KiB
C
/*
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* Copyright 2022 The ChromiumOS Authors.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/__assert.h>
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LOG_MODULE_REGISTER(soc_it8xxx2_ilm, CONFIG_LOG_DEFAULT_LEVEL);
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/*
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* Instruction Local Memory (ILM) support for IT8xxx2.
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*
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* IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
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* Data Local Memory (ILM or DLM). Addresses from which instructions will be fetched by the CPU
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* *must* be in the Flash memory space: it is not permitted to execute from RAM addresses, only
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* through ILM mappings into RAM.
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*
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* When a RAM block is configured as ILM, accesses to addresses matching the corresponding Scratch
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* SRAM address register (SCARn{H,M,L}) are redirected to the corresponding ILM block in RAM.
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* If SCAR0 (corresponding to ILM0) has the value 0x8021532 and ILM0 is enabled, then instruction
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* fetches from the memory range 0x8021532..0x8022532 will be redirected to physical addresses
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* 0x80100000..0x80101000 (the first 4k block of RAM).
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*
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* Instruction fetch from Flash is normally cacheable, but configuring ILM for a region makes that
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* address range non-cacheable (which is appropriate because Flash has high latency but RAM is
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* essentially the same speed as cache).
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*/
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extern const uint8_t __ilm_flash_start[];
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extern const uint8_t __ilm_flash_end[];
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extern uint8_t __ilm_ram_start[];
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extern uint8_t __ilm_ram_end[];
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#define ILM_BLOCK_SIZE 0x1000
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BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must be a power of two");
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#define FLASH_BASE CONFIG_FLASH_BASE_ADDRESS
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#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define ILM_NODE DT_NODELABEL(ilm)
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#define SCARH_ENABLE BIT(3)
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#define SCARH_ADDR_BIT19 BIT(7)
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/*
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* SCAR registers contain 20-bit addresses in three registers, with one set
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* of SCAR registers for each ILM block that may be configured.
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*/
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struct scar_reg {
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/* Bits 0..7 of address; SCARnL */
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uint8_t l;
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/* Bits 8..15 of address; SCARnM */
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uint8_t m;
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/* Bits 16..18 and 19 of address, plus the enable bit for the entire SCAR; SCARnH */
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uint8_t h;
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};
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struct ilm_config {
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volatile struct scar_reg *scar_regs[CONFIG_ILM_MAX_SIZE / 4];
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};
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bool it8xxx2_is_ilm_configured(void)
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{
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return device_is_ready(DEVICE_DT_GET(ILM_NODE));
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}
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static bool __maybe_unused is_block_aligned(const void *const p)
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{
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return ((uintptr_t)p & (ILM_BLOCK_SIZE - 1)) == 0;
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}
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static int it8xxx2_configure_ilm_block(const struct ilm_config *const config, void *ram_addr,
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const void *flash_addr, const size_t copy_sz)
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{
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if ((uintptr_t)ram_addr < RAM_BASE) {
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return -EFAULT; /* Not in RAM */
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}
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const int dirmap_index = ((uintptr_t)ram_addr - RAM_BASE) / ILM_BLOCK_SIZE;
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if (dirmap_index >= ARRAY_SIZE(config->scar_regs)) {
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return -EFAULT; /* Past the end of RAM */
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}
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BUILD_ASSERT((FLASH_BASE & GENMASK(19, 0)) == 0,
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"Flash is assumed to be aligned to SCAR register width");
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if (((uintptr_t)flash_addr - FLASH_BASE) & ~GENMASK(19, 0)) {
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return -EFAULT; /* Address doesn't fit in the SCAR */
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}
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if (!is_block_aligned(flash_addr)) {
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/* Bits 0..11 of SCAR can be programmed but ILM only works if they're zero */
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return -EFAULT;
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}
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LOG_DBG("Enabling ILM%d %p -> %p, copy %d", dirmap_index, flash_addr, ram_addr, copy_sz);
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volatile struct scar_reg *const scar = config->scar_regs[dirmap_index];
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int irq_key = irq_lock();
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/* Ensure scratch RAM for block data access is enabled */
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scar->h = SCARH_ENABLE;
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/* Copy block contents from flash into RAM */
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memcpy(ram_addr, flash_addr, copy_sz);
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/* Program SCAR */
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scar->l = (uintptr_t)flash_addr & GENMASK(7, 0);
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scar->m = ((uintptr_t)flash_addr & GENMASK(15, 8)) >> 8;
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uint8_t scarh_value = ((uintptr_t)flash_addr & GENMASK(18, 16)) >> 16;
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if ((uintptr_t)flash_addr & BIT(19)) {
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scarh_value |= SCARH_ADDR_BIT19;
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}
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scar->h = scarh_value;
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irq_unlock(irq_key);
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return 0;
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}
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static int it8xxx2_ilm_init(const struct device *dev)
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{
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/* Invariants enforced by the linker script */
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__ASSERT(is_block_aligned(__ilm_ram_start),
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"ILM physical base address (%p) must be 4k-aligned", __ilm_ram_start);
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__ASSERT(is_block_aligned(__ilm_flash_start),
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"ILM flash base address (%p) must be 4k-aligned", __ilm_flash_start);
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__ASSERT_NO_MSG((uintptr_t)__ilm_ram_end >= (uintptr_t)__ilm_ram_start &&
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(uintptr_t)__ilm_flash_end >= (uintptr_t)__ilm_flash_start);
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LOG_DBG("ILM init %p-%p -> %p-%p", __ilm_flash_start, __ilm_flash_end, __ilm_ram_start,
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__ilm_ram_end);
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for (uintptr_t block_base = (uintptr_t)__ilm_ram_start;
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block_base < (uintptr_t)__ilm_ram_end; block_base += ILM_BLOCK_SIZE) {
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uintptr_t flash_base =
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(uintptr_t)__ilm_flash_start + (block_base - (uintptr_t)__ilm_ram_start);
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/*
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* Part of the target RAM block might be used for non-code data; avoid overwriting
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* it by only copying as much data as the ILM flash region contains.
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*/
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size_t used_size = MIN((uintptr_t)__ilm_flash_end - flash_base, ILM_BLOCK_SIZE);
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int rv = it8xxx2_configure_ilm_block(dev->config, (void *)block_base,
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(const void *)flash_base, used_size);
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if (rv) {
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LOG_ERR("Unable to configure ILM block %p: %d", (void *)flash_base, rv);
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return rv;
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}
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}
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return 0;
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}
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#define SCAR_REG(n) (volatile struct scar_reg *)DT_REG_ADDR_BY_IDX(ILM_NODE, n)
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static const struct ilm_config ilm_config = {
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.scar_regs = {
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/* SCAR0 SRAM 4KB */
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SCAR_REG(0),
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SCAR_REG(1),
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SCAR_REG(2),
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SCAR_REG(3),
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SCAR_REG(4),
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SCAR_REG(5),
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SCAR_REG(6),
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SCAR_REG(7),
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SCAR_REG(8),
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SCAR_REG(9),
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SCAR_REG(10),
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SCAR_REG(11),
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SCAR_REG(12),
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SCAR_REG(13),
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SCAR_REG(14),
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/*
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* Except for CONFIG_SOC_IT81202CX and CONFIG_SOC_IT81302CX
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* maximum ILM size are 60KB, the ILM size of other varients
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* are equal to the SRAM size.
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*/
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#if (CONFIG_ILM_MAX_SIZE == 256)
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/* SCAR15 SRAM 4KB */
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SCAR_REG(15),
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/* SCAR16 SRAM 16KB */
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SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), SCAR_REG(16),
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/* SCAR17 SRAM 16KB */
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SCAR_REG(17), SCAR_REG(17), SCAR_REG(17), SCAR_REG(17),
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/* SCAR18 SRAM 16KB */
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SCAR_REG(18), SCAR_REG(18), SCAR_REG(18), SCAR_REG(18),
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/* SCAR19 SRAM 16KB */
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SCAR_REG(19), SCAR_REG(19), SCAR_REG(19), SCAR_REG(19),
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/* SCAR20 SRAM 32KB */
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SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
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SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
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/* SCAR21 SRAM 32KB */
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SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
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SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
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/* SCAR22 SRAM 32KB */
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SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
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SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
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/* SCAR23 SRAM 32KB */
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SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23),
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SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23)
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#endif
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}};
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BUILD_ASSERT(ARRAY_SIZE(ilm_config.scar_regs) * ILM_BLOCK_SIZE == KB(CONFIG_ILM_MAX_SIZE),
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"Wrong number of SCAR registers defined for RAM size");
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DEVICE_DT_DEFINE(ILM_NODE, &it8xxx2_ilm_init, NULL, NULL, &ilm_config, PRE_KERNEL_1, 0, NULL);
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