105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
/*
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* Copyright (c) 2013-2015 Wind River Systems, Inc.
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* Copyright (c) 2016 Intel Corporation.
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* Copyright (c) 2017 Justin Watson
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* Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
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* Copyright (c) 2023 Basalte bv
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Atmel SAM4E MCU series initialization code
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*
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* This module provides routines to initialize and support board-level hardware
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* for the Atmel SAM4E series processor.
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*/
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#include <soc.h>
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#include <soc_pmc.h>
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#include <soc_supc.h>
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/**
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* @brief Setup various clock on SoC at boot time.
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*
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* Setup the SoC clocks according to section 28.12 in datasheet.
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*
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* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
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* It is assumed that the relevant registers are at their reset value.
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*/
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static ALWAYS_INLINE void clock_init(void)
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{
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/* Switch the main clock to the internal OSC with 12MHz */
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soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
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/* Switch MCK (Master Clock) to the main clock */
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soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
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EFC->EEFC_FMR = EEFC_FMR_FWS(0);
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soc_pmc_enable_clock_failure_detector();
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
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soc_supc_slow_clock_select_crystal_osc();
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}
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
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/*
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* Setup main external crystal oscillator.
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*/
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/* We select maximum setup time.
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* While start up time could be shortened
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* this optimization is not deemed
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* critical now.
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*/
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soc_pmc_switch_mainck_to_xtal(false, 0xff);
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}
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/*
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* Set FWS (Flash Wait State) value before increasing Master Clock
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* (MCK) frequency. Look at table 44.73 in the SAM4E datasheet.
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* This is set to the highest number of read cycles because it won't
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* hurt lower clock frequencies. However, a high frequency with too
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* few read cycles could cause flash read problems. FWS 5 (6 cycles)
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* is the safe setting for all of this SoCs usable frequencies.
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*/
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EFC->EEFC_FMR = EEFC_FMR_FWS(5);
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/*
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* Setup PLLA
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*/
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soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
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CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
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/*
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* Final setup of the Master Clock
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*/
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/* prescaler has to be set before PLL lock */
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soc_pmc_mck_set_prescaler(1);
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/* Select PLL as Master Clock source. */
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soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
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/* Disable internal fast RC if we have an external crystal oscillator */
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
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soc_pmc_osc_disable_fastrc();
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}
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}
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void soc_reset_hook(void)
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{
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
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/*
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* Instruct CPU to enter Wait mode instead of Sleep mode to
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* keep Processor Clock (HCLK) and thus be able to debug
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* CPU using JTAG.
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*/
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soc_pmc_enable_waitmode();
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}
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/* Setup system clocks. */
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clock_init();
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}
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