zephyr

History

Gil Pitney c73a1eb806 cc3220sf: Add support for the TI CC3220SF SoC The CC3220SF is a replacement for the CC3200 SoC, comprising a network coprocessor and Cortex-M4 MPU. This leverages the CC3220 SDK driver peripheral library in ROM, and some files built from ext/hal/ti/. Jira: ZEP-1958 Change-Id: I892b212c178e05d84ff1d716dde593ced653ae6d Signed-off-by: Gil Pitney <gil.pitney@linaro.org>		2017-04-28 15:06:41 -05:00
..
Kconfig.defconfig.cc3200	cc3200: Resolve DTS fixup.	2017-04-04 17:55:12 -05:00
Kconfig.defconfig.cc3220sf	cc3220sf: Add support for the TI CC3220SF SoC	2017-04-28 15:06:41 -05:00
Kconfig.defconfig.series	cc3200: Resolve DTS fixup.	2017-04-04 17:55:12 -05:00
Kconfig.series	arm: systick: Some SoCs do not have systick	2016-11-27 19:39:26 +00:00
Kconfig.soc	cc3220sf: Add support for the TI CC3220SF SoC	2017-04-28 15:06:41 -05:00
Makefile	…
README	cc3220sf: Add support for the TI CC3220SF SoC	2017-04-28 15:06:41 -05:00
linker.ld	…
soc.c	cc3220sf: Add support for the TI CC3220SF SoC	2017-04-28 15:06:41 -05:00
soc.h	license: Replace Apache boilerplate with SPDX tag	2017-01-19 03:50:58 +00:00

README

CC3200 Board and Bootloader info taken from:
* http://www.ti.com.cn/cn/lit/ug/swru367c/swru367c.pdf
* http://www.ti.com/lit/ug/swru369c/swru369c.pdf

CC3220 Info taken from:
* http://www.ti.com/lit/ug/swru465/swru465.pdf

Notes for CC3200:
 * CC3200 has no integrated flash Memory.
 * TI bootloader takes first 16Kb of the 256Kb SRAM, so app must start at
   0x20004000.  CC3200 Kconfig must set SRAM size to 240Kb or less, since
   Zephyr computes TOP_OF_MEMORY (used for stack) based on SRAM_BASE_ADDRESS
   + SRAM_SIZE.

Notes for CC3220SF:
 * Text must start at 0x800 offset in flash.  The first 0x800 bytes are
   reserved for the flash header.
 * See CONFIG_TEXT_SECTION_OFFSET.