360 lines
8.7 KiB
C
360 lines
8.7 KiB
C
/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <string.h>
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#include <zephyr/device.h>
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#include <soc.h>
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#include <zephyr/drivers/ipm.h>
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#include <zephyr/irq.h>
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#if defined(CONFIG_IPM_IMX_REV2)
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#define DT_DRV_COMPAT nxp_imx_mu_rev2
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#include "fsl_mu.h"
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#else
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#define DT_DRV_COMPAT nxp_imx_mu
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#include <mu_imx.h>
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#endif
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#define MU(config) ((MU_Type *)config->base)
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#if ((CONFIG_IPM_IMX_MAX_DATA_SIZE % 4) != 0)
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#error CONFIG_IPM_IMX_MAX_DATA_SIZE is invalid
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#endif
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#define IMX_IPM_DATA_REGS (CONFIG_IPM_IMX_MAX_DATA_SIZE / 4)
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struct imx_mu_config {
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MU_Type *base;
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void (*irq_config_func)(const struct device *dev);
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};
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struct imx_mu_data {
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ipm_callback_t callback;
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void *user_data;
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};
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#if defined(CONFIG_IPM_IMX_REV2)
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/*!
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* @brief Check RX full status.
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*
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* This function checks the specific receive register full status.
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*
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* @param base Register base address for the module.
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* @param index RX register index to check.
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* @retval true RX register is full.
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* @retval false RX register is not full.
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*/
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static inline bool MU_IsRxFull(MU_Type *base, uint32_t index)
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{
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switch (index) {
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case 0:
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return (bool)(MU_GetStatusFlags(base) & kMU_Rx0FullFlag);
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case 1:
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return (bool)(MU_GetStatusFlags(base) & kMU_Rx1FullFlag);
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case 2:
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return (bool)(MU_GetStatusFlags(base) & kMU_Rx2FullFlag);
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case 3:
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return (bool)(MU_GetStatusFlags(base) & kMU_Rx3FullFlag);
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default:
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/* This shouldn't happen */
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assert(false);
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return false;
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}
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}
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/*!
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* @brief Check TX empty status.
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*
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* This function checks the specific transmit register empty status.
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*
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* @param base Register base address for the module.
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* @param index TX register index to check.
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* @retval true TX register is empty.
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* @retval false TX register is not empty.
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*/
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static inline bool MU_IsTxEmpty(MU_Type *base, uint32_t index)
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{
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switch (index) {
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case 0:
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return (bool)(MU_GetStatusFlags(base) & kMU_Tx0EmptyFlag);
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case 1:
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return (bool)(MU_GetStatusFlags(base) & kMU_Tx1EmptyFlag);
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case 2:
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return (bool)(MU_GetStatusFlags(base) & kMU_Tx2EmptyFlag);
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case 3:
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return (bool)(MU_GetStatusFlags(base) & kMU_Tx3EmptyFlag);
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default:
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/* This shouldn't happen */
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assert(false);
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return false;
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}
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}
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#endif
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static void imx_mu_isr(const struct device *dev)
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{
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const struct imx_mu_config *config = dev->config;
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MU_Type *base = MU(config);
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struct imx_mu_data *data = dev->data;
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uint32_t data32[IMX_IPM_DATA_REGS];
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uint32_t status_reg;
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int32_t id;
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int32_t i;
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bool all_registers_full;
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status_reg = base->SR >>= MU_SR_RFn_SHIFT;
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for (id = CONFIG_IPM_IMX_MAX_ID_VAL; id >= 0; id--) {
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if (status_reg & 0x1U) {
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/*
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* Check if all receive registers are full. If not,
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* it is violation of the protocol (status register
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* are set earlier than all receive registers).
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* Do not read any of the registers in such situation.
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*/
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all_registers_full = true;
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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if (!MU_IsRxFull(base,
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(id * IMX_IPM_DATA_REGS) + i)) {
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all_registers_full = false;
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break;
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}
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}
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if (all_registers_full) {
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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#if defined(CONFIG_IPM_IMX_REV2)
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data32[i] = MU_ReceiveMsg(base,
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(id * IMX_IPM_DATA_REGS) + i);
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#else
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MU_ReceiveMsg(base,
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(id * IMX_IPM_DATA_REGS) + i,
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&data32[i]);
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#endif
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}
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if (data->callback) {
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data->callback(dev, data->user_data,
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(uint32_t)id,
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&data32[0]);
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}
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}
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}
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status_reg >>= IMX_IPM_DATA_REGS;
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F
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* Store immediate overlapping exception return operation
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* might vector to incorrect interrupt. For Cortex-M7, if
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* core speed much faster than peripheral register write
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* speed, the peripheral interrupt flags may be still set
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* after exiting ISR, this results to the same error similar
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* with errata 838869.
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*/
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#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
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__DSB();
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#endif
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}
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static int imx_mu_ipm_send(const struct device *dev, int wait, uint32_t id,
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const void *data, int size)
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{
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const struct imx_mu_config *config = dev->config;
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MU_Type *base = MU(config);
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uint32_t data32[IMX_IPM_DATA_REGS];
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#if !IS_ENABLED(CONFIG_IPM_IMX_REV2)
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mu_status_t status;
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#endif
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int i;
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if (id > CONFIG_IPM_IMX_MAX_ID_VAL) {
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return -EINVAL;
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}
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if (size > CONFIG_IPM_IMX_MAX_DATA_SIZE) {
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return -EMSGSIZE;
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}
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/* Actual message is passing using 32 bits registers */
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memcpy(data32, data, size);
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#if defined(CONFIG_IPM_IMX_REV2)
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if (wait) {
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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MU_SendMsgNonBlocking(base, id * IMX_IPM_DATA_REGS + i,
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data32[i]);
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}
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while (!MU_IsTxEmpty(base,
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(id * IMX_IPM_DATA_REGS) + IMX_IPM_DATA_REGS - 1)) {
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}
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} else {
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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if (MU_IsTxEmpty(base, id * IMX_IPM_DATA_REGS + i)) {
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MU_SendMsg(base, id * IMX_IPM_DATA_REGS + i,
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data32[i]);
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} else {
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return -EBUSY;
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}
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}
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}
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#else
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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status = MU_TrySendMsg(base, id * IMX_IPM_DATA_REGS + i,
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data32[i]);
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if (status == kStatus_MU_TxNotEmpty) {
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return -EBUSY;
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}
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}
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if (wait) {
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while (!MU_IsTxEmpty(base,
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(id * IMX_IPM_DATA_REGS) + IMX_IPM_DATA_REGS - 1)) {
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}
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}
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#endif
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return 0;
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}
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static int imx_mu_ipm_max_data_size_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return CONFIG_IPM_IMX_MAX_DATA_SIZE;
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}
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static uint32_t imx_mu_ipm_max_id_val_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return CONFIG_IPM_IMX_MAX_ID_VAL;
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}
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static void imx_mu_ipm_register_callback(const struct device *dev,
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ipm_callback_t cb,
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void *user_data)
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{
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struct imx_mu_data *driver_data = dev->data;
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driver_data->callback = cb;
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driver_data->user_data = user_data;
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}
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static int imx_mu_ipm_set_enabled(const struct device *dev, int enable)
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{
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const struct imx_mu_config *config = dev->config;
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MU_Type *base = MU(config);
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#if defined(CONFIG_IPM_IMX_REV2)
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#if CONFIG_IPM_IMX_MAX_DATA_SIZE_4
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if (enable) {
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MU_EnableInterrupts(base, kMU_Rx0FullInterruptEnable);
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MU_EnableInterrupts(base, kMU_Rx1FullInterruptEnable);
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MU_EnableInterrupts(base, kMU_Rx2FullInterruptEnable);
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MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable);
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} else {
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MU_DisableInterrupts(base, kMU_Rx0FullInterruptEnable);
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MU_DisableInterrupts(base, kMU_Rx1FullInterruptEnable);
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MU_DisableInterrupts(base, kMU_Rx2FullInterruptEnable);
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MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable);
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}
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#elif CONFIG_IPM_IMX_MAX_DATA_SIZE_8
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if (enable) {
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MU_EnableInterrupts(base, kMU_Rx1FullInterruptEnable);
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MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable);
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} else {
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MU_DisableInterrupts(base, kMU_Rx1FullInterruptEnable);
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MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable);
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}
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#elif CONFIG_IPM_IMX_MAX_DATA_SIZE_16
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if (enable) {
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MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable);
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} else {
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MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable);
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}
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#else
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#error "CONFIG_IPM_IMX_MAX_DATA_SIZE_n is not set"
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#endif
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#else
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#if CONFIG_IPM_IMX_MAX_DATA_SIZE_4
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if (enable) {
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MU_EnableRxFullInt(base, 0U);
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MU_EnableRxFullInt(base, 1U);
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MU_EnableRxFullInt(base, 2U);
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MU_EnableRxFullInt(base, 3U);
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} else {
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MU_DisableRxFullInt(base, 0U);
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MU_DisableRxFullInt(base, 1U);
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MU_DisableRxFullInt(base, 2U);
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MU_DisableRxFullInt(base, 3U);
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}
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#elif CONFIG_IPM_IMX_MAX_DATA_SIZE_8
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if (enable) {
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MU_EnableRxFullInt(base, 1U);
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MU_EnableRxFullInt(base, 3U);
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} else {
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MU_DisableRxFullInt(base, 1U);
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MU_DisableRxFullInt(base, 3U);
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}
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#elif CONFIG_IPM_IMX_MAX_DATA_SIZE_16
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if (enable) {
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MU_EnableRxFullInt(base, 3U);
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} else {
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MU_DisableRxFullInt(base, 3U);
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}
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#else
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#error "CONFIG_IPM_IMX_MAX_DATA_SIZE_n is not set"
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#endif
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#endif
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return 0;
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}
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static int imx_mu_init(const struct device *dev)
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{
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const struct imx_mu_config *config = dev->config;
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MU_Init(MU(config));
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config->irq_config_func(dev);
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return 0;
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}
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static const struct ipm_driver_api imx_mu_driver_api = {
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.send = imx_mu_ipm_send,
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.register_callback = imx_mu_ipm_register_callback,
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.max_data_size_get = imx_mu_ipm_max_data_size_get,
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.max_id_val_get = imx_mu_ipm_max_id_val_get,
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.set_enabled = imx_mu_ipm_set_enabled
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};
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/* Config MU */
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static void imx_mu_config_func_b(const struct device *dev);
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static const struct imx_mu_config imx_mu_b_config = {
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.base = (MU_Type *)DT_INST_REG_ADDR(0),
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.irq_config_func = imx_mu_config_func_b,
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};
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static struct imx_mu_data imx_mu_b_data;
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DEVICE_DT_INST_DEFINE(0,
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&imx_mu_init,
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NULL,
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&imx_mu_b_data, &imx_mu_b_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_mu_driver_api);
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static void imx_mu_config_func_b(const struct device *dev)
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{
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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imx_mu_isr, DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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}
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