229 lines
6.3 KiB
C
229 lines
6.3 KiB
C
/*
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* Copyright (c) 2022 Vestas Wind Systems A/S
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* Copyright (c) 2022 Blue Clover
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/can.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <stm32_ll_rcc.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include "can_mcan.h"
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LOG_MODULE_REGISTER(can_stm32h7, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT st_stm32h7_fdcan
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struct can_stm32h7_config {
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mm_reg_t base;
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void (*config_irq)(void);
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const struct pinctrl_dev_config *pcfg;
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struct stm32_pclken pclken;
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};
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static int can_stm32h7_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_stm32h7_config *stm32h7_config = mcan_config->custom;
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return can_mcan_sys_read_reg(stm32h7_config->base, reg, val);
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}
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static int can_stm32h7_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_stm32h7_config *stm32h7_config = mcan_config->custom;
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return can_mcan_sys_write_reg(stm32h7_config->base, reg, val);
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}
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static int can_stm32h7_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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const uint32_t rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
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ARG_UNUSED(dev);
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if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
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LOG_ERR("Can't read core clock");
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return -EIO;
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}
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*rate = rate_tmp;
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LOG_DBG("rate=%d", *rate);
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return 0;
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}
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static int can_stm32h7_clock_enable(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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int ret;
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LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PLL1Q);
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if (!device_is_ready(clk)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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ret = clock_control_on(clk, (clock_control_subsys_t)&stm32h7_cfg->pclken);
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if (ret != 0) {
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LOG_ERR("failure enabling clock");
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return ret;
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}
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if (!LL_RCC_PLL1Q_IsEnabled()) {
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LOG_ERR("PLL1Q clock must be enabled!");
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return -EIO;
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}
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return 0;
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}
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static int can_stm32h7_init(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
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struct can_mcan_data *mcan_data = dev->data;
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const uintptr_t mrba = POINTER_TO_UINT(mcan_data->msg_ram);
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int ret;
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/* Configure dt provided device signals when available */
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ret = pinctrl_apply_state(stm32h7_cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret != 0) {
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LOG_ERR("CAN pinctrl setup failed (%d)", ret);
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return ret;
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}
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ret = can_stm32h7_clock_enable(dev);
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if (ret != 0) {
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return ret;
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}
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ret = can_mcan_configure_message_ram(dev, mrba);
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if (ret != 0) {
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return ret;
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}
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ret = can_mcan_init(dev);
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if (ret != 0) {
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return ret;
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}
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stm32h7_cfg->config_irq();
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return 0;
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}
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static const struct can_driver_api can_stm32h7_driver_api = {
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.get_capabilities = can_mcan_get_capabilities,
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.start = can_mcan_start,
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.stop = can_mcan_stop,
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.set_mode = can_mcan_set_mode,
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.set_timing = can_mcan_set_timing,
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.send = can_mcan_send,
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.add_rx_filter = can_mcan_add_rx_filter,
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.remove_rx_filter = can_mcan_remove_rx_filter,
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.get_state = can_mcan_get_state,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_mcan_recover,
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#endif
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.get_core_clock = can_stm32h7_get_core_clock,
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.get_max_bitrate = can_mcan_get_max_bitrate,
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.get_max_filters = can_mcan_get_max_filters,
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.set_state_change_callback = can_mcan_set_state_change_callback,
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/* Timing limits are per the STM32H7 Reference Manual (RM0433 Rev 7),
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* section 56.5.7, FDCAN nominal bit timing and prescaler register
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* (FDCAN_NBTP).
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*/
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.timing_min = {
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.sjw = 0x01,
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.prop_seg = 0x00,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_max = {
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.sjw = 0x80,
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.prop_seg = 0x00,
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.phase_seg1 = 0x100,
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.phase_seg2 = 0x80,
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.prescaler = 0x200
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},
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#ifdef CONFIG_CAN_FD_MODE
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.set_timing_data = can_mcan_set_timing_data,
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/* Data timing limits are per the STM32H7 Reference Manual
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* (RM0433 Rev 7), section 56.5.3, FDCAN data bit timing and prescaler
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* register (FDCAN_DBTP).
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*/
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.timing_data_min = {
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.sjw = 0x01,
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.prop_seg = 0x00,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_data_max = {
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.sjw = 0x10,
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.prop_seg = 0x00,
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.phase_seg1 = 0x20,
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.phase_seg2 = 0x10,
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.prescaler = 0x20
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}
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#endif
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};
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#define CAN_STM32H7_MCAN_INIT(n) \
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static void stm32h7_mcan_irq_config_##n(void); \
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\
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static const struct can_stm32h7_config can_stm32h7_cfg_##n = { \
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.base = (mm_reg_t)DT_INST_REG_ADDR_BY_NAME(n, m_can), \
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.config_irq = stm32h7_mcan_irq_config_##n, \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.pclken = { \
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.enr = DT_INST_CLOCKS_CELL(n, bits), \
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.bus = DT_INST_CLOCKS_CELL(n, bus), \
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}, \
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}; \
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\
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static const struct can_mcan_config can_mcan_cfg_##n = \
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CAN_MCAN_DT_CONFIG_INST_GET(n, &can_stm32h7_cfg_##n, \
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can_stm32h7_read_reg, \
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can_stm32h7_write_reg); \
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\
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static struct can_mcan_data can_mcan_data_##n = \
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CAN_MCAN_DATA_INITIALIZER((struct can_mcan_msg_sram *) \
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DT_INST_REG_ADDR_BY_NAME(n, message_ram), NULL); \
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\
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DEVICE_DT_INST_DEFINE(n, &can_stm32h7_init, NULL, \
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&can_mcan_data_##n, \
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&can_mcan_cfg_##n, \
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POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
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&can_stm32h7_driver_api); \
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\
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static void stm32h7_mcan_irq_config_##n(void) \
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{ \
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LOG_DBG("Enable CAN inst" #n " IRQ"); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, line_0, irq), \
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DT_INST_IRQ_BY_NAME(n, line_0, priority), \
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can_mcan_line_0_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(n, line_0, irq)); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, line_1, irq), \
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DT_INST_IRQ_BY_NAME(n, line_1, priority), \
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can_mcan_line_1_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(n, line_1, irq)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(CAN_STM32H7_MCAN_INIT)
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