516 lines
13 KiB
C
516 lines
13 KiB
C
/*
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <init.h>
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#include <device.h>
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#include <soc.h>
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#include <uart.h>
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#include <arch/arm/cortex_m/cmsis.h>
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/*
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* UART PL011 register map structure
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*/
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struct pl011_regs {
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u32_t dr; /* data register */
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union {
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u32_t rsr;
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u32_t ecr;
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};
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u32_t reserved_0[4];
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u32_t fr; /* flags register */
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u32_t reserved_1;
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u32_t ilpr;
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u32_t ibrd;
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u32_t fbrd;
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u32_t lcr_h;
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u32_t cr;
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u32_t ifls;
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u32_t imsc;
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u32_t ris;
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u32_t mis;
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u32_t icr;
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u32_t dmacr;
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};
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/* Device data structure */
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struct pl011_data {
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u32_t baud_rate; /* Baud rate */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t irq_cb;
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void *irq_cb_data;
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#endif
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};
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#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
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/* PL011 Uart Flags Register */
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#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
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#define PL011_FR_DSR BIT(1) /* data set ready - inverted */
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#define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */
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#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
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#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
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#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
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#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
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#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
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#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
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/* PL011 Integer baud rate register */
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#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
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/* PL011 Fractional baud rate register */
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#define PL011_FBRD_BAUD_DIVFRAC 0x3f
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#define PL011_FBRD_WIDTH 6u
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/* PL011 Receive status register / error clear register */
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#define PL011_RSR_ECR_FE BIT(0) /* framing error */
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#define PL011_RSR_ECR_PE BIT(1) /* parity erorr */
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#define PL011_RSR_ECR_BE BIT(2) /* break error */
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#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
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#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
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PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
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/* PL011 Line Control Register */
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#define PL011_LCRH_BRK BIT(0) /* send break */
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#define PL011_LCRH_PEN BIT(1) /* enable parity */
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#define PL011_LCRH_EPS BIT(2) /* select even parity */
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#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
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#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
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#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
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#define PL011_LCRH_WLEN_WIDTH 2
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#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
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#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
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#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
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PL011_LCRH_SPS | \
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PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, PL011_LCRH_WLEN_SHIFT))
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#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
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#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
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#define PL011_LCRH_PARITY_NONE (0)
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/* PL011 Control Register */
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#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
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#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
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#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
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#define PL011_CR_LBE BIT(7) /* loop back enable */
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#define PL011_CR_TXE BIT(8) /* transmit enable */
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#define PL011_CR_RXE BIT(9) /* receive enable */
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#define PL011_CR_DTR BIT(10) /* data transmit ready */
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#define PL011_CR_RTS BIT(11) /* request to send */
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#define PL011_CR_Out1 BIT(12)
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#define PL011_CR_Out2 BIT(13)
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#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable */
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#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable */
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/* PL011 Interrupt Fifo Level Select Register */
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#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
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#define PL011_IFLS_TXIFLSEL_WIDTH 3
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#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
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#define PL011_IFLS_RXIFLSEL_WIDTH 3
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/* PL011 Interrupt Mask Set/Clear Register */
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#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
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#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
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#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
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#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
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#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
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#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
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#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt mask */
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#define PL011_IMSC_FEIM BIT(7) /* framine error interrupt mask */
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#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask */
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#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask */
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#define PL011_IMSC_OEIM BIT(10) /* overrun error interrutpt mask */
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#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
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PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
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PL011_IMSC_OEIM)
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#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
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PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
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PL011_IMSC_RIMIM | PL011_IMSC_CTSMIM | \
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PL011_IMSC_DCDMIM | PL011_IMSC_DSRMIM | \
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PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
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PL011_IMSC_RTIM)
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#define DEV_CFG(dev) \
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((const struct uart_device_config * const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct pl011_data *)(dev)->driver_data)
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#define PL011_REGS(dev) \
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((volatile struct pl011_regs *)(DEV_CFG(dev))->base)
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static void pl011_enable(struct device *dev)
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{
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PL011_REGS(dev)->cr |= PL011_CR_UARTEN;
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}
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static void pl011_disable(struct device *dev)
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{
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PL011_REGS(dev)->cr &= ~PL011_CR_UARTEN;
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}
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static void pl011_enable_fifo(struct device *dev)
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{
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PL011_REGS(dev)->lcr_h |= PL011_LCRH_FEN;
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}
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static void pl011_disable_fifo(struct device *dev)
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{
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PL011_REGS(dev)->lcr_h &= ~PL011_LCRH_FEN;
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}
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static int pl011_set_baudrate(struct device *dev,
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u32_t clk, u32_t baudrate)
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{
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/* Avoiding float calculations, bauddiv is left shifted by 6 */
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u64_t bauddiv = (((u64_t)clk) << PL011_FBRD_WIDTH)
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/ (baudrate * 16U);
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/* Valid bauddiv value
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* uart_clk (min) >= 16 x baud_rate (max)
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* uart_clk (max) <= 16 x 65535 x baud_rate (min)
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*/
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if ((bauddiv < (1u << PL011_FBRD_WIDTH))
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|| (bauddiv > (65535u << PL011_FBRD_WIDTH))) {
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return -EINVAL;
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}
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PL011_REGS(dev)->ibrd = bauddiv >> PL011_FBRD_WIDTH;
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PL011_REGS(dev)->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
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__DMB();
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/* In order to internally update the contents of ibrd or fbrd, a
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* lcr_h write must always be performed at the end
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* ARM DDI 0183F, Pg 3-13
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*/
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PL011_REGS(dev)->lcr_h = PL011_REGS(dev)->lcr_h;
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return 0;
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}
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static bool pl011_is_readable(struct device *dev)
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{
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if ((PL011_REGS(dev)->cr & PL011_CR_UARTEN) &&
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(PL011_REGS(dev)->cr & PL011_CR_RXE) &&
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((PL011_REGS(dev)->fr & PL011_FR_RXFE) == 0U)) {
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return true;
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}
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return false;
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}
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static int pl011_poll_in(struct device *dev, unsigned char *c)
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{
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if (!pl011_is_readable(dev)) {
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return -1;
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}
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/* got a character */
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*c = (unsigned char)PL011_REGS(dev)->dr;
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return PL011_REGS(dev)->rsr & PL011_RSR_ERROR_MASK;
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}
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static void pl011_poll_out(struct device *dev,
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unsigned char c)
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{
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/* Wait for space in FIFO */
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while (PL011_REGS(dev)->fr & PL011_FR_TXFF) {
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; /* Wait */
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}
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/* Send a character */
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PL011_REGS(dev)->dr = (u32_t)c;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int pl011_fifo_fill(struct device *dev,
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const u8_t *tx_data, int len)
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{
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u8_t num_tx = 0U;
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while (!(PL011_REGS(dev)->fr & PL011_FR_TXFF) &&
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(len - num_tx > 0)) {
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PL011_REGS(dev)->dr = tx_data[num_tx++];
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}
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return num_tx;
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}
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static int pl011_fifo_read(struct device *dev,
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u8_t *rx_data, const int len)
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{
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u8_t num_rx = 0U;
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while ((len - num_rx > 0) &&
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!(PL011_REGS(dev)->fr & PL011_FR_RXFE)) {
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rx_data[num_rx++] = PL011_REGS(dev)->dr;
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}
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return num_rx;
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}
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static void pl011_irq_tx_enable(struct device *dev)
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{
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PL011_REGS(dev)->imsc |= PL011_IMSC_TXIM;
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}
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static void pl011_irq_tx_disable(struct device *dev)
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{
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PL011_REGS(dev)->imsc &= ~PL011_IMSC_TXIM;
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}
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static int pl011_irq_tx_complete(struct device *dev)
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{
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/* check for TX FIFO empty */
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return PL011_REGS(dev)->fr & PL011_FR_TXFE;
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}
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static int pl011_irq_tx_ready(struct device *dev)
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{
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return ((PL011_REGS(dev)->cr & PL011_CR_TXE) &&
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(PL011_REGS(dev)->imsc & PL011_IMSC_TXIM) &&
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pl011_irq_tx_complete(dev));
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}
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static void pl011_irq_rx_enable(struct device *dev)
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{
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PL011_REGS(dev)->imsc |= PL011_IMSC_RXIM |
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PL011_IMSC_RTIM;
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}
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static void pl011_irq_rx_disable(struct device *dev)
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{
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PL011_REGS(dev)->imsc &= ~(PL011_IMSC_RXIM |
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PL011_IMSC_RTIM);
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}
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static int pl011_irq_rx_ready(struct device *dev)
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{
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return ((PL011_REGS(dev)->cr & PL011_CR_RXE) &&
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(PL011_REGS(dev)->imsc & PL011_IMSC_RXIM) &&
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(!(PL011_REGS(dev)->fr & PL011_FR_RXFE)));
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}
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static void pl011_irq_err_enable(struct device *dev)
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{
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/* enable framing, parity, break, and overrun */
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PL011_REGS(dev)->imsc |= PL011_IMSC_ERROR_MASK;
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}
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static void pl011_irq_err_disable(struct device *dev)
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{
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PL011_REGS(dev)->imsc &= ~PL011_IMSC_ERROR_MASK;
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}
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static int pl011_irq_is_pending(struct device *dev)
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{
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return pl011_irq_rx_ready(dev) || pl011_irq_tx_ready(dev);
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}
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static int pl011_irq_update(struct device *dev)
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{
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return 1;
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}
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static void pl011_irq_callback_set(struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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DEV_DATA(dev)->irq_cb = cb;
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DEV_DATA(dev)->irq_cb_data = cb_data;
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}
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static const struct uart_driver_api pl011_driver_api = {
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.poll_in = pl011_poll_in,
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.poll_out = pl011_poll_out,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = pl011_fifo_fill,
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.fifo_read = pl011_fifo_read,
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.irq_tx_enable = pl011_irq_tx_enable,
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.irq_tx_disable = pl011_irq_tx_disable,
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.irq_tx_ready = pl011_irq_tx_ready,
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.irq_rx_enable = pl011_irq_rx_enable,
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.irq_rx_disable = pl011_irq_rx_disable,
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.irq_tx_complete = pl011_irq_tx_complete,
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.irq_rx_ready = pl011_irq_rx_ready,
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.irq_err_enable = pl011_irq_err_enable,
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.irq_err_disable = pl011_irq_err_disable,
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.irq_is_pending = pl011_irq_is_pending,
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.irq_update = pl011_irq_update,
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.irq_callback_set = pl011_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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static int pl011_init(struct device *dev)
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{
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int ret;
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u32_t lcrh;
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const struct uart_device_config *config = dev->config->config_info;
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/* disable the uart */
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pl011_disable(dev);
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pl011_disable_fifo(dev);
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/* Set baud rate */
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ret = pl011_set_baudrate(dev, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
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DEV_DATA(dev)->baud_rate);
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if (ret != 0) {
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return ret;
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}
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/* Setting the default character format */
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lcrh = PL011_REGS(dev)->lcr_h & ~(PL011_LCRH_FORMAT_MASK);
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lcrh &= ~(BIT(0) | BIT(7));
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lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
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PL011_REGS(dev)->lcr_h = lcrh;
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/* Enabling the FIFOs */
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pl011_enable_fifo(dev);
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/* initialize all IRQs as masked */
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PL011_REGS(dev)->imsc = 0U;
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PL011_REGS(dev)->icr = PL011_IMSC_MASK_ALL;
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PL011_REGS(dev)->dmacr = 0U;
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__ISB();
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PL011_REGS(dev)->cr &= ~(BIT(14) | BIT(15) | BIT(1));
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PL011_REGS(dev)->cr |= PL011_CR_RXE | PL011_CR_TXE;
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__ISB();
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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config->irq_config_func(dev);
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#endif
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pl011_enable(dev);
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return 0;
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}
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void pl011_isr(void *arg)
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{
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struct device *dev = arg;
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struct pl011_data *data = DEV_DATA(dev);
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/* Verify if the callback has been registered */
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if (data->irq_cb) {
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data->irq_cb(data->irq_cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#ifdef CONFIG_UART_PL011_PORT0
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void pl011_irq_config_func_0(struct device *dev);
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#endif
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static struct uart_device_config pl011_cfg_port_0 = {
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.base = (u8_t *)DT_PL011_PORT0_BASE_ADDRESS,
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.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = pl011_irq_config_func_0,
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#endif
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};
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static struct pl011_data pl011_data_port_0 = {
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.baud_rate = DT_PL011_PORT0_BAUD_RATE,
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};
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DEVICE_AND_API_INIT(pl011_port_0,
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DT_PL011_PORT0_NAME,
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&pl011_init,
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&pl011_data_port_0,
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&pl011_cfg_port_0, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&pl011_driver_api);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void pl011_irq_config_func_0(struct device *dev)
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{
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IRQ_CONNECT(DT_PL011_PORT0_IRQ_TX,
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DT_PL011_PORT0_IRQ_PRI,
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pl011_isr,
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DEVICE_GET(pl011_port_0),
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0);
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irq_enable(DT_PL011_PORT0_IRQ_TX);
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IRQ_CONNECT(DT_PL011_PORT0_IRQ_RX,
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DT_PL011_PORT0_IRQ_PRI,
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pl011_isr,
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DEVICE_GET(pl011_port_0),
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0);
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irq_enable(DT_PL011_PORT0_IRQ_RX);
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IRQ_CONNECT(DT_PL011_PORT0_IRQ_RXTIM,
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DT_PL011_PORT0_IRQ_PRI,
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pl011_isr,
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DEVICE_GET(pl011_port_0),
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0);
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irq_enable(DT_PL011_PORT0_IRQ_RXTIM);
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}
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#endif
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#endif /* CONFIG_UART_PL011_PORT0 */
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#ifdef CONFIG_UART_PL011_PORT1
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void pl011_irq_config_func_1(struct device *dev);
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#endif
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static struct uart_device_config pl011_cfg_port_1 = {
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.base = (u8_t *)DT_PL011_PORT1_BASE_ADDRESS,
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.sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = pl011_irq_config_func_1,
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#endif
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};
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static struct pl011_data pl011_data_port_1 = {
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.baud_rate = DT_PL011_PORT1_BAUD_RATE,
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};
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DEVICE_AND_API_INIT(pl011_port_1,
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DT_PL011_PORT1_NAME,
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&pl011_init,
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&pl011_data_port_1,
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&pl011_cfg_port_1, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&pl011_driver_api);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void pl011_irq_config_func_1(struct device *dev)
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{
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IRQ_CONNECT(DT_PL011_PORT1_IRQ_TX,
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DT_PL011_PORT1_IRQ_PRI,
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pl011_isr,
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DEVICE_GET(pl011_port_1),
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0);
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irq_enable(DT_PL011_PORT1_IRQ_TX);
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IRQ_CONNECT(DT_PL011_PORT1_IRQ_RX,
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DT_PL011_PORT1_IRQ_PRI,
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pl011_isr,
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DEVICE_GET(pl011_port_1),
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0);
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irq_enable(DT_PL011_PORT1_IRQ_RX);
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IRQ_CONNECT(DT_PL011_PORT1_IRQ_RXTIM,
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DT_PL011_PORT1_IRQ_PRI,
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pl011_isr,
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DEVICE_GET(pl011_port_1),
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0);
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irq_enable(DT_PL011_PORT1_IRQ_RXTIM);
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}
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#endif
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#endif /* CONFIG_UART_PL011_PORT1 */
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