294 lines
6.5 KiB
C
294 lines
6.5 KiB
C
/*
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* Copyright (c) 2017 Google LLC.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <soc.h>
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#include <interrupt_controller/sam0_eic.h>
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#include "gpio_utils.h"
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struct gpio_sam0_config {
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PortGroup *regs;
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#ifdef CONFIG_SAM0_EIC
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u8_t id;
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#endif
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};
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struct gpio_sam0_data {
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#ifdef CONFIG_SAM0_EIC
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sys_slist_t callbacks;
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#endif
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};
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#define DEV_CFG(dev) \
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((const struct gpio_sam0_config *const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct gpio_sam0_data *const)(dev)->driver_data)
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#ifdef CONFIG_SAM0_EIC
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static void gpio_sam0_isr(u32_t pins, void *arg)
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{
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struct device *const dev = (struct device *) arg;
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struct gpio_sam0_data *const data = DEV_DATA(dev);
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gpio_fire_callbacks(&data->callbacks, dev, pins);
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}
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#endif
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static int gpio_sam0_config(struct device *dev, int access_op, u32_t pin,
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int flags)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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PortGroup *regs = config->regs;
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u32_t mask = 1 << pin;
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bool is_out = (flags & GPIO_DIR_MASK) == GPIO_DIR_OUT;
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int pud = flags & GPIO_PUD_MASK;
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PORT_PINCFG_Type pincfg;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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/* Builds the configuration and writes it in one go */
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pincfg.reg = 0;
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pincfg.bit.INEN = 1;
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/* Direction */
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if (is_out) {
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regs->DIRSET.bit.DIRSET = mask;
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} else {
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regs->DIRCLR.bit.DIRCLR = mask;
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}
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/* Pull up / pull down */
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if (is_out && pud != GPIO_PUD_NORMAL) {
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return -ENOTSUP;
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}
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switch (pud) {
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case GPIO_PUD_NORMAL:
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break;
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case GPIO_PUD_PULL_UP:
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pincfg.bit.PULLEN = 1;
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regs->OUTSET.reg = mask;
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break;
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case GPIO_PUD_PULL_DOWN:
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pincfg.bit.PULLEN = 1;
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regs->OUTCLR.reg = mask;
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break;
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default:
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return -ENOTSUP;
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}
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#ifdef CONFIG_SAM0_EIC
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if ((flags & GPIO_INT) != 0) {
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/*
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* The EIC requires setting the pin to function A, so do
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* that as part of the interrupt enable, so that the API
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* is consistent.
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*/
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pincfg.bit.PMUXEN = 1;
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if (pin & 1) {
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regs->PMUX[pin / 2].bit.PMUXO = PORT_PMUX_PMUXE_A_Val;
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} else {
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regs->PMUX[pin / 2].bit.PMUXE = PORT_PMUX_PMUXE_A_Val;
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}
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enum sam0_eic_trigger trigger;
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if ((flags & GPIO_INT_DOUBLE_EDGE) != 0) {
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trigger = SAM0_EIC_BOTH;
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} else if (flags & GPIO_INT_EDGE) {
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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trigger = SAM0_EIC_RISING;
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} else {
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trigger = SAM0_EIC_FALLING;
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}
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} else {
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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trigger = SAM0_EIC_HIGH;
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} else {
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trigger = SAM0_EIC_LOW;
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}
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}
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int retval = sam0_eic_acquire(config->id, pin, trigger,
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(flags & GPIO_INT_DEBOUNCE) != 0,
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gpio_sam0_isr, dev);
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if (retval != 0) {
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return retval;
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}
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} else {
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sam0_eic_release(config->id, pin);
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/*
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* Pinmux disabled by the config set, so this
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* correctly inverts the EIC enable part above.
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*/
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}
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#else
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if ((flags & GPIO_INT) != 0) {
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return -ENOTSUP;
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}
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#endif
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/* Write the now-built pin configuration */
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regs->PINCFG[pin] = pincfg;
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if ((flags & GPIO_POL_MASK) != GPIO_POL_NORMAL) {
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_sam0_write(struct device *dev, int access_op, u32_t pin,
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u32_t value)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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u32_t mask = 1 << pin;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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/* TODO(mlhx): support GPIO_ACCESS_BY_PORT */
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return -ENOTSUP;
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}
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if (value != 0U) {
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config->regs->OUTSET.bit.OUTSET = mask;
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} else {
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config->regs->OUTCLR.bit.OUTCLR = mask;
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}
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return 0;
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}
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static int gpio_sam0_read(struct device *dev, int access_op, u32_t pin,
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u32_t *value)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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u32_t bits;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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/* TODO(mlhx): support GPIO_ACCESS_BY_PORT */
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return -ENOTSUP;
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}
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bits = config->regs->IN.bit.IN;
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*value = (bits >> pin) & 1;
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return 0;
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}
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#ifdef CONFIG_SAM0_EIC
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int gpio_sam0_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_sam0_data *const data = DEV_DATA(dev);
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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int gpio_sam0_enable_callback(struct device *dev, int access_op, u32_t pin)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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return sam0_eic_enable_interrupt(config->id, pin);
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}
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int gpio_sam0_disable_callback(struct device *dev, int access_op, u32_t pin)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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return sam0_eic_disable_interrupt(config->id, pin);
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}
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u32_t gpio_sam0_get_pending_int(struct device *dev)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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return sam0_eic_interrupt_pending(config->id);
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}
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#endif
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static const struct gpio_driver_api gpio_sam0_api = {
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.config = gpio_sam0_config,
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.write = gpio_sam0_write,
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.read = gpio_sam0_read,
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#ifdef CONFIG_SAM0_EIC
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.manage_callback = gpio_sam0_manage_callback,
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.enable_callback = gpio_sam0_enable_callback,
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.disable_callback = gpio_sam0_disable_callback,
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.get_pending_int = gpio_sam0_get_pending_int,
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#endif
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};
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static int gpio_sam0_init(struct device *dev) { return 0; }
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/* Port A */
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#if DT_ATMEL_SAM0_GPIO_PORT_A_BASE_ADDRESS
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static const struct gpio_sam0_config gpio_sam0_config_0 = {
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.regs = (PortGroup *)DT_ATMEL_SAM0_GPIO_PORT_A_BASE_ADDRESS,
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#ifdef CONFIG_SAM0_EIC
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.id = 0,
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#endif
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};
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static struct gpio_sam0_data gpio_sam0_data_0;
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DEVICE_AND_API_INIT(gpio_sam0_0, DT_ATMEL_SAM0_GPIO_PORT_A_LABEL,
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gpio_sam0_init, &gpio_sam0_data_0, &gpio_sam0_config_0,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam0_api);
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#endif
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/* Port B */
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#if DT_ATMEL_SAM0_GPIO_PORT_B_BASE_ADDRESS
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static const struct gpio_sam0_config gpio_sam0_config_1 = {
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.regs = (PortGroup *)DT_ATMEL_SAM0_GPIO_PORT_B_BASE_ADDRESS,
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#ifdef CONFIG_SAM0_EIC
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.id = 1,
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#endif
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};
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static struct gpio_sam0_data gpio_sam0_data_1;
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DEVICE_AND_API_INIT(gpio_sam0_1, DT_ATMEL_SAM0_GPIO_PORT_B_LABEL,
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gpio_sam0_init, &gpio_sam0_data_1, &gpio_sam0_config_1,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam0_api);
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#endif
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/* Port C */
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#if DT_ATMEL_SAM0_GPIO_PORT_C_BASE_ADDRESS
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static const struct gpio_sam0_config gpio_sam0_config_2 = {
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.regs = (PortGroup *)DT_ATMEL_SAM0_GPIO_PORT_C_BASE_ADDRESS,
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#ifdef CONFIG_SAM0_EIC
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.id = 2,
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#endif
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};
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static struct gpio_sam0_data gpio_sam0_data_2;
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DEVICE_AND_API_INIT(gpio_sam0_2, DT_ATMEL_SAM0_GPIO_PORT_C_LABEL,
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gpio_sam0_init, &gpio_sam0_data_2, &gpio_sam0_config_2,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam0_api);
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#endif
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