81 lines
1.4 KiB
Plaintext
81 lines
1.4 KiB
Plaintext
/*
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* Copyright (c) 2023 Cypress Semiconductor Corporation.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Configure pin control bias mode for uart2 pins */
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&p3_1_scb2_uart_tx {
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drive-push-pull;
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};
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&p3_0_scb2_uart_rx {
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input-enable;
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};
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&p3_2_scb2_uart_rts {
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drive-push-pull;
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};
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&p3_3_scb2_uart_cts {
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input-enable;
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};
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/* Configure pin control bias mode for uart5 pins */
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&p5_1_scb5_uart_tx {
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drive-push-pull;
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};
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&p5_0_scb5_uart_rx {
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input-enable;
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};
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/* Configure pin control bias mode for i2c3 pins */
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&p6_0_scb3_i2c_scl {
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drive-open-drain;
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input-enable;
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};
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&p6_1_scb3_i2c_sda {
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drive-open-drain;
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input-enable;
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};
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&pinctrl {
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/* Configure pin control bias mode for SDIO */
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p2_5_sdio_clk: p2_5_sdio_clk {
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pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_14)>;
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drive-push-pull;
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input-enable;
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};
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p2_4_sdio_cmd: p2_4_sdio_cmd {
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pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_14)>;
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drive-push-pull;
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input-enable;
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};
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p2_0_sdio_data0: p2_0_sdio_data0 {
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pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_14)>;
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drive-push-pull;
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input-enable;
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};
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p2_1_sdio_data1: p2_1_sdio_data1 {
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pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_14)>;
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drive-push-pull;
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input-enable;
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};
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p2_2_sdio_data2: p2_2_sdio_data2 {
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pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_14)>;
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drive-push-pull;
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input-enable;
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};
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p2_3_sdio_data3: p2_3_sdio_data3 {
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pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_14)>;
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drive-push-pull;
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input-enable;
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};
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};
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