215 lines
5.9 KiB
C
215 lines
5.9 KiB
C
/* board.h - board configuration macros for the ia32_pci platform */
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/*
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* Copyright (c) 2013-2015, Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* DESCRIPTION
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* This header file is used to specify and describe board-level aspects for
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* the 'ia32_pci' platform.
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*/
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#ifndef __INCboardh
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#define __INCboardh
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#include <misc/util.h>
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#ifndef _ASMLANGUAGE
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#include <device.h>
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#include <drivers/rand32.h>
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#endif
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#ifdef CONFIG_IOAPIC
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#include <drivers/ioapic.h>
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#ifdef CONFIG_SERIAL_INTERRUPT_LEVEL
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#ifdef CONFIG_SERIAL_INTERRUPT_LOW
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#define UART_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
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#else
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#define UART_IOAPIC_FLAGS (IOAPIC_LEVEL)
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#endif
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#else /* edge triggered interrupt */
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#ifdef CONFIG_SERIAL_INTERRUPT_LOW
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/* generate interrupt on falling edge */
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#define UART_IOAPIC_FLAGS (IOAPIC_LOW)
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#else
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/* generate interrupt on raising edge */
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#define UART_IOAPIC_FLAGS (0)
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#endif
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#endif
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#endif
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#define NUM_STD_IRQS 16 /* number of "standard" IRQs on an x86 platform */
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#define INT_VEC_IRQ0 0x20 /* Vector number for IRQ0 */
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/* serial port (aka COM port) information */
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#define COM1_BAUD_RATE 115200
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#define COM2_BAUD_RATE 115200
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#define COM2_INT_LVL 0x11 /* COM2 connected to IRQ17 */
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#define UART_REG_ADDR_INTERVAL 4 /* address diff of adjacent regs. */
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#define UART_XTAL_FREQ (2764800 * 16)
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/* uart configuration settings */
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/* Generic definitions */
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#define CONFIG_UART_PCI_VENDOR_ID 0x8086
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#define CONFIG_UART_PCI_DEVICE_ID 0x0936
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#define CONFIG_UART_PCI_BUS 0
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#define CONFIG_UART_PCI_DEV 20
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#define CONFIG_UART_PORT_0_FUNCTION 1
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#define CONFIG_UART_PORT_1_FUNCTION 5
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#define CONFIG_UART_PCI_BAR 0
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#define CONFIG_UART_BAUDRATE COM1_BAUD_RATE
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#ifndef _ASMLANGUAGE
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extern struct device * const uart_devs[];
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#endif
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#if defined(CONFIG_UART_CONSOLE)
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#define CONFIG_UART_CONSOLE_IRQ COM2_INT_LVL
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#define CONFIG_UART_CONSOLE_INT_PRI 3
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#define UART_CONSOLE_DEV (uart_devs[CONFIG_UART_CONSOLE_INDEX])
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#endif /* CONFIG_UART_CONSOLE */
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#ifdef CONFIG_GPIO_DW_0
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#if defined(CONFIG_GPIO_DW_0_FALLING_EDGE)
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#define GPIO_DW_0_IRQ_IOAPIC_FLAGS (IOAPIC_EDGE | IOAPIC_LOW)
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#elif defined(CONFIG_GPIO_DW_0_RISING_EDGE)
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#define GPIO_DW_0_IRQ_IOAPIC_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
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#elif defined(CONFIG_GPIO_DW_0_LEVEL_HIGH)
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#define GPIO_DW_0_IRQ_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH)
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#elif defined(CONFIG_GPIO_DW_0_LEVEL_LOW)
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#define GPIO_DW_0_IRQ_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
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#endif
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#endif /* GPIO_DW_0 */
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/* Bluetooth UART definitions */
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#if defined(CONFIG_BLUETOOTH_UART)
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#define CONFIG_BLUETOOTH_UART_INDEX 1
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#define CONFIG_BLUETOOTH_UART_IRQ COM2_INT_LVL
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#define CONFIG_BLUETOOTH_UART_INT_PRI 3
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#define CONFIG_BLUETOOTH_UART_FREQ UART_XTAL_FREQ
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#define CONFIG_BLUETOOTH_UART_BAUDRATE CONFIG_UART_BAUDRATE
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#define BT_UART_DEV (uart_devs[CONFIG_BLUETOOTH_UART_INDEX])
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#endif /* CONFIG_BLUETOOTH_UART */
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#ifdef CONFIG_I2C_DW
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#include <drivers/ioapic.h>
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#if defined(CONFIG_I2C_DW_IRQ_FALLING_EDGE)
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#define I2C_DW_IRQ_IOAPIC_FLAGS (IOAPIC_EDGE | IOAPIC_LOW)
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#elif defined(CONFIG_I2C_DW_IRQ_RISING_EDGE)
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#define I2C_DW_IRQ_IOAPIC_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
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#elif defined(CONFIG_I2C_DW_IRQ_LEVEL_HIGH)
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#define I2C_DW_IRQ_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH)
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#elif defined(CONFIG_I2C_DW_IRQ_LEVEL_LOW)
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#define I2C_DW_IRQ_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
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#endif
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#endif /* CONFIG_I2C_DW_0 */
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#ifdef CONFIG_SPI_INTEL
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#if defined(CONFIG_SPI_INTEL_FALLING_EDGE)
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#define SPI_INTEL_IRQ_IOAPIC_FLAGS (IOAPIC_EDGE | IOAPIC_LOW)
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#elif defined(CONFIG_SPI_INTEL_RISING_EDGE)
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#define SPI_INTEL_IRQ_IOAPIC_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
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#elif defined(CONFIG_SPI_INTEL_LEVEL_HIGH)
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#define SPI_INTEL_IRQ_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH)
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#elif defined(CONFIG_SPI_INTEL_LEVEL_LOW)
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#define SPI_INTEL_IRQ_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
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#endif
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#endif /* CONFIG_SPI_INTEL */
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/*
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* The irq_connect() API connects to a (virtualized) IRQ and the
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* associated interrupt controller is programmed with the allocated vector.
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* The Quark board virtualizes IRQs as follows:
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*
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* - The first CONFIG_IOAPIC_NUM_RTES IRQs are provided by the IOAPIC
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* - The remaining IRQs are provided by the LOAPIC.
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*
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* Thus, for example, if the IOAPIC supports 24 IRQs:
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*
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* - IRQ0 to IRQ23 map to IOAPIC IRQ0 to IRQ23
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* - IRQ24 to IRQ29 map to LOAPIC LVT entries as follows:
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*
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* IRQ24 -> LOAPIC_TIMER
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* IRQ25 -> LOAPIC_THERMAL
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* IRQ26 -> LOAPIC_PMC
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* IRQ27 -> LOAPIC_LINT0
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* IRQ28 -> LOAPIC_LINT1
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* IRQ29 -> LOAPIC_ERROR
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*/
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/* PCI definitions */
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#define PCI_BUS_NUMBERS 2
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#define PCI_CTRL_ADDR_REG 0xCF8
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#define PCI_CTRL_DATA_REG 0xCFC
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#define PCI_INTA 1
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#define PCI_INTB 2
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#define PCI_INTC 3
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#define PCI_INTD 4
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/**
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*
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* @brief Convert PCI interrupt PIN to IRQ
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*
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* The routine uses "standard design consideration" and implies that
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* INTA (pin 1) -> IRQ 16
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* INTB (pin 2) -> IRQ 17
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* INTC (pin 3) -> IRQ 18
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* INTD (pin 4) -> IRQ 19
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*
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* @return IRQ number, -1 if the result is incorrect
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*
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*/
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static inline int pci_pin2irq(int pin)
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{
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if ((pin < PCI_INTA) || (pin > PCI_INTD))
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return -1;
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return NUM_STD_IRQS + pin - 1;
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}
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/**
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*
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* @brief Convert IRQ to PCI interrupt pin
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*
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* @return pin number, -1 if the result is incorrect
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*
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*/
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static inline int pci_irq2pin(int irq)
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{
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if ((irq < NUM_STD_IRQS) || (irq > NUM_STD_IRQS + PCI_INTD - 1))
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return -1;
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return irq - NUM_STD_IRQS + 1;
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}
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extern void _SysIntVecProgram(unsigned int vector, unsigned int);
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#endif /* __INCboardh */
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