62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/* cache.c - cache manipulation */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* DESCRIPTION
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* This module contains functions for manipulation caches.
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <misc/util.h>
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#ifdef CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED
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#if (CONFIG_CACHE_LINE_SIZE == 0)
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#error Cannot use this implementation with a cache line size of 0
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#endif
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/**
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*
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* @brief Flush a page to main memory
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*
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* No alignment is required for either <virt> or <size>, but since
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* sys_cache_flush() iterates on the cache lines, a cache line alignment for
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* both is optimal.
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*
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* The cache line size is specified via the CONFIG_CACHE_LINE_SIZE kconfig
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* option.
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*
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* @return N/A
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*/
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void sys_cache_flush(vaddr_t virt, size_t size)
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{
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int end;
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size = ROUND_UP(size, CONFIG_CACHE_LINE_SIZE);
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end = virt + size;
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for (; virt < end; virt += CONFIG_CACHE_LINE_SIZE) {
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__asm__ volatile("clflush %0;\n\t" : : "m"(virt));
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}
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__asm__ volatile("mfence;\n\t");
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}
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#endif /* CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED */
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