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zephyr/dts/arm/nxp/nxp_imx7d_m4.dtsi

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/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <arm/armv7-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/rdc/imx_rdc.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4";
reg = <0>;
};
};
soc {
ddr_code: code@10000000 {
compatible = "nxp,imx-code-bus";
reg = <0x10000000 0xfff0000>;
label = "DDR CODE";
};
ddr_sys: memory@80000000 {
device_type = "memory";
compatible = "nxp,imx-sys-bus";
reg = <0x80000000 0x60000000>;
label = "DDR SYSTEM";
};
tcml_code: code@1fff8000 {
compatible = "nxp,imx-itcm";
reg = <0x1fff8000 DT_SIZE_K(32)>;
label = "TCML CODE";
};
tcmu_sys: memory@20000000 {
compatible = "nxp,imx-dtcm";
reg = <0x20000000 DT_SIZE_K(32)>;
label = "TCMU SYSTEM";
};
ocram_code: code@900000 {
compatible = "nxp,imx-code-bus";
reg = <0x00900000 DT_SIZE_K(128)>;
label = "OCRAM CODE";
};
ocram_sys: memory@20200000 {
device_type = "memory";
compatible = "nxp,imx-sys-bus";
reg = <0x20200000 DT_SIZE_K(128)>;
label = "OCRAM SYSTEM";
};
ocram_s_code: code@20180000 {
compatible = "nxp,imx-code-bus";
reg = <0x20180000 DT_SIZE_K(32)>;
label = "OCRAM_S CODE";
};
ocram_s_sys: memory@180000 {
device_type = "memory";
compatible = "nxp,imx-sys-bus";
reg = <0x00180000 DT_SIZE_K(32)>;
label = "OCRAM_S SYSTEM";
};
gpio1: gpio@30200000 {
compatible = "nxp,imx-gpio";
reg = <0x30200000 0x10000>;
interrupts = <64 0>, <65 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio@30210000 {
compatible = "nxp,imx-gpio";
reg = <0x30210000 0x10000>;
interrupts = <66 0>, <67 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio@30220000 {
compatible = "nxp,imx-gpio";
reg = <0x30220000 0x10000>;
interrupts = <68 0>, <69 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio@30230000 {
compatible = "nxp,imx-gpio";
reg = <0x30230000 0x10000>;
interrupts = <70 0>, <71 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio@30240000 {
compatible = "nxp,imx-gpio";
reg = <0x30240000 0x10000>;
interrupts = <72 0>, <73 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_5";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio@30250000 {
compatible = "nxp,imx-gpio";
reg = <0x30250000 0x10000>;
interrupts = <74 0>, <75 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_6";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio@30260000 {
compatible = "nxp,imx-gpio";
reg = <0x30260000 0x10000>;
interrupts = <76 0>, <77 0>;
label = "GPIO_7";
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* For now only uart2 is supported and
* tested with the serial driver
*/
uart1: uart@30860000 {
compatible = "nxp,imx-uart";
reg = <0x30860000 0x10000>;
interrupts = <26 3>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_1";
status = "disabled";
};
uart2: uart@30890000 {
compatible = "nxp,imx-uart";
reg = <0x30890000 0x10000>;
interrupts = <27 3>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_2";
status = "disabled";
};
uart3: uart@30880000 {
compatible = "nxp,imx-uart";
reg = <0x30880000 0x10000>;
interrupts = <28 3>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_3";
status = "disabled";
};
uart4: uart@30a60000 {
compatible = "nxp,imx-uart";
reg = <0x30a60000 0x10000>;
interrupts = <29 3>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_4";
status = "disabled";
};
uart5: uart@30a70000 {
compatible = "nxp,imx-uart";
reg = <0x30a70000 0x10000>;
interrupts = <30 3>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_5";
status = "disabled";
};
uart6: uart@30a80000 {
compatible = "nxp,imx-uart";
reg = <0x30a80000 0x10000>;
interrupts = <16 3>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_6";
status = "disabled";
};
uart7: uart@30a90000 {
compatible = "nxp,imx-uart";
reg = <0x30a90000 0x10000>;
interrupts = <126 3>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_7";
status = "disabled";
};
mub:mu@30ab0000 {
compatible = "nxp,imx-mu";
reg = <0x30ab0000 0x4000>;
interrupts = <97 0>;
rdc = <RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)>;
label = "MU_B";
status = "disabled";
};
i2c1: i2c@30a20000 {
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a20000 0x10000>;
interrupts = <35 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "I2C_1";
status = "disabled";
};
i2c2: i2c@30a30000 {
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a30000 0x10000>;
interrupts = <36 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "I2C_2";
status = "disabled";
};
i2c3: i2c@30a40000 {
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a40000 0x10000>;
interrupts = <37 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "I2C_3";
status = "disabled";
};
i2c4: i2c@30a50000 {
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a50000 0x10000>;
interrupts = <38 0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "I2C_4";
status = "disabled";
};
pwm1: pwm@30660000 {
compatible = "fsl,imx7d-pwm";
reg = <0x30660000 0x10000>;
interrupts = <81 0>;
prescaler = <0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "PWM_1";
status = "disabled";
#pwm-cells = <2>;
};
pwm2: pwm@30670000 {
compatible = "fsl,imx7d-pwm";
reg = <0x30670000 0x10000>;
interrupts = <82 0>;
prescaler = <0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "PWM_2";
status = "disabled";
#pwm-cells = <2>;
};
pwm3: pwm@30680000 {
compatible = "fsl,imx7d-pwm";
reg = <0x30680000 0x10000>;
interrupts = <83 0>;
prescaler = <0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "PWM_3";
status = "disabled";
#pwm-cells = <2>;
};
pwm4: pwm@30690000 {
compatible = "fsl,imx7d-pwm";
reg = <0x30690000 0x10000>;
interrupts = <84 0>;
prescaler = <0>;
rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "PWM_4";
status = "disabled";
#pwm-cells = <2>;
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
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