656 lines
17 KiB
C
656 lines
17 KiB
C
/*
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* Copyright (c) 2020, FrankLi Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ovti_ov7725
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#include <zephyr.h>
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#include <device.h>
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#include <sys/byteorder.h>
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#include <drivers/video.h>
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#include <drivers/i2c.h>
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#include <drivers/gpio.h>
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#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(ov7725);
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#define OV7725_REVISION 0x7721U
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#define OV7725_GAIN 0x00U
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#define OV7725_BLUE 0x01U
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#define OV7725_RED 0x02U
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#define OV7725_GREEN 0x03U
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#define OV7725_BAVG 0x05U
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#define OV7725_GAVG 0x06U
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#define OV7725_RAVG 0x07U
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#define OV7725_AECH 0x08U
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#define OV7725_COM2 0x09U
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#define OV7725_PID 0x0AU
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#define OV7725_VER 0x0BU
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#define OV7725_COM3 0x0CU
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#define OV7725_COM4 0x0DU
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#define OV7725_COM5 0x0EU
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#define OV7725_COM6 0x0FU
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#define OV7725_AEC 0x10U
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#define OV7725_CLKRC 0x11U
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#define OV7725_COM7 0x12U
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#define OV7725_COM8 0x13U
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#define OV7725_COM9 0x14U
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#define OV7725_COM10 0x15U
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#define OV7725_REG16 0x16U
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#define OV7725_HSTART 0x17U
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#define OV7725_HSIZE 0x18U
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#define OV7725_VSTART 0x19U
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#define OV7725_VSIZE 0x1AU
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#define OV7725_PSHFT 0x1BU
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#define OV7725_MIDH 0x1CU
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#define OV7725_MIDL 0x1DU
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#define OV7725_LAEC 0x1FU
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#define OV7725_COM11 0x20U
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#define OV7725_BDBASE 0x22U
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#define OV7725_BDMSTEP 0x23U
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#define OV7725_AEW 0x24U
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#define OV7725_AEB 0x25U
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#define OV7725_VPT 0x26U
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#define OV7725_REG28 0x28U
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#define OV7725_HOUTSIZE 0x29U
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#define OV7725_EXHCH 0x2AU
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#define OV7725_EXHCL 0x2BU
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#define OV7725_VOUTSIZE 0x2CU
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#define OV7725_ADVFL 0x2DU
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#define OV7725_ADVFH 0x2EU
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#define OV7725_YAVE 0x2FU
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#define OV7725_LUMHTH 0x30U
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#define OV7725_LUMLTH 0x31U
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#define OV7725_HREF 0x32U
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#define OV7725_DM_LNL 0x33U
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#define OV7725_DM_LNH 0x34U
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#define OV7725_ADOFF_B 0x35U
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#define OV7725_ADOFF_R 0x36U
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#define OV7725_ADOFF_GB 0x37U
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#define OV7725_ADOFF_GR 0x38U
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#define OV7725_OFF_B 0x39U
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#define OV7725_OFF_R 0x3AU
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#define OV7725_OFF_GB 0x3BU
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#define OV7725_OFF_GR 0x3CU
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#define OV7725_COM12 0x3DU
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#define OV7725_COM13 0x3EU
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#define OV7725_COM14 0x3FU
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#define OV7725_COM16 0x41U
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#define OV7725_TGT_B 0x42U
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#define OV7725_TGT_R 0x43U
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#define OV7725_TGT_GB 0x44U
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#define OV7725_TGT_GR 0x45U
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#define OV7725_LC_CTR 0x46U
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#define OV7725_LC_XC 0x47U
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#define OV7725_LC_YC 0x48U
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#define OV7725_LC_COEF 0x49U
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#define OV7725_LC_RADI 0x4AU
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#define OV7725_LC_COEFB 0x4BU
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#define OV7725_LC_COEFR 0x4CU
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#define OV7725_FIXGAIN 0x4DU
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#define OV7725_AREF1 0x4FU
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#define OV7725_AREF6 0x54U
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#define OV7725_UFIX 0x60U
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#define OV7725_VFIX 0x61U
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#define OV7725_AWBB_BLK 0x62U
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#define OV7725_AWB_CTRL0 0x63U
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#define OV7725_DSP_CTRL1 0x64U
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#define OV7725_DSP_CTRL2 0x65U
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#define OV7725_DSP_CTRL3 0x66U
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#define OV7725_DSP_CTRL4 0x67U
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#define OV7725_AWB_BIAS 0x68U
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#define OV7725_AWB_CTRL1 0x69U
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#define OV7725_AWB_CTRL2 0x6AU
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#define OV7725_AWB_CTRL3 0x6BU
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#define OV7725_AWB_CTRL4 0x6CU
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#define OV7725_AWB_CTRL5 0x6DU
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#define OV7725_AWB_CTRL6 0x6EU
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#define OV7725_AWB_CTRL7 0x6FU
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#define OV7725_AWB_CTRL8 0x70U
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#define OV7725_AWB_CTRL9 0x71U
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#define OV7725_AWB_CTRL10 0x72U
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#define OV7725_AWB_CTRL11 0x73U
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#define OV7725_AWB_CTRL12 0x74U
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#define OV7725_AWB_CTRL13 0x75U
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#define OV7725_AWB_CTRL14 0x76U
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#define OV7725_AWB_CTRL15 0x77U
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#define OV7725_AWB_CTRL16 0x78U
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#define OV7725_AWB_CTRL17 0x79U
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#define OV7725_AWB_CTRL18 0x7AU
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#define OV7725_AWB_CTRL19 0x7BU
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#define OV7725_AWB_CTRL20 0x7CU
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#define OV7725_AWB_CTRL21 0x7DU
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#define OV7725_GAM1 0x7EU
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#define OV7725_GAM2 0x7FU
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#define OV7725_GAM3 0x80U
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#define OV7725_GAM4 0x81U
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#define OV7725_GAM5 0x82U
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#define OV7725_GAM6 0x83U
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#define OV7725_GAM7 0x84U
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#define OV7725_GAM8 0x85U
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#define OV7725_GAM9 0x86U
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#define OV7725_GAM10 0x87U
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#define OV7725_GAM11 0x88U
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#define OV7725_GAM12 0x89U
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#define OV7725_GAM13 0x8AU
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#define OV7725_GAM14 0x8BU
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#define OV7725_GAM15 0x8CU
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#define OV7725_SLOP 0x8DU
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#define OV7725_DNSTH 0x8EU
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#define OV7725_EDGE0 0x8FU
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#define OV7725_EDGE1 0x90U
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#define OV7725_DNSOFF 0x91U
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#define OV7725_EDGE2 0x92U
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#define OV7725_EDGE3 0x93U
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#define OV7725_MTX1 0x94U
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#define OV7725_MTX2 0x95U
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#define OV7725_MTX3 0x96U
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#define OV7725_MTX4 0x97U
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#define OV7725_MTX5 0x98U
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#define OV7725_MTX6 0x99U
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#define OV7725_MTX_CTRL 0x9AU
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#define OV7725_BRIGHT 0x9BU
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#define OV7725_CNST 0x9CU
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#define OV7725_UVADJ0 0x9EU
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#define OV7725_UVADJ1 0x9FU
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#define OV7725_SCAL0 0xA0U
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#define OV7725_SCAL1 0xA1U
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#define OV7725_SCAL2 0xA2U
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#define OV7725_SDE 0xA6U
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#define OV7725_USAT 0xA7U
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#define OV7725_VSAT 0xA8U
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#define OV7725_HUECOS 0xA9U
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#define OV7725_HUESIN 0xAAU
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#define OV7725_SIGN 0xABU
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#define OV7725_DSPAUTO 0xACU
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#define OV7725_COM10_VSYNC_NEG_MASK BIT(1)
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#define OV7725_COM10_HREF_REVERSE_MASK BIT(3)
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#define OV7725_COM10_PCLK_REVERSE_MASK BIT(4)
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#define OV7725_COM10_PCLK_OUT_MASK BIT(5)
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#define OV7725_COM10_DATA_NEG_MASK BIT(7)
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struct ov7725_data {
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const struct device *i2c;
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const struct device *reset_gpio;
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uint8_t reset_pin;
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gpio_dt_flags_t reset_flags;
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struct video_format fmt;
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uint8_t i2c_addr;
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};
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struct ov7725_clock {
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uint32_t input_clk;
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uint32_t framerate;
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uint8_t clkrc; /*!< Register CLKRC. */
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uint8_t com4; /*!< Register COM4. */
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uint8_t dm_lnl; /*!< Register DM_LNL. */
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};
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struct ov7725_pixel_format {
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uint32_t pixel_format;
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uint8_t com7;
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};
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struct ov7725_reg {
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uint8_t addr;
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uint8_t value;
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};
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static const struct ov7725_clock ov7725_clock_configs[] = {
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{ .input_clk = 24000000, .framerate = 30,
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.clkrc = 0x01, .com4 = 0x41, .dm_lnl = 0x00 },
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{ .input_clk = 24000000, .framerate = 15,
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.clkrc = 0x03, .com4 = 0x41, .dm_lnl = 0x00 },
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{ .input_clk = 24000000, .framerate = 25,
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.clkrc = 0x01, .com4 = 0x41, .dm_lnl = 0x66 },
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{ .input_clk = 24000000, .framerate = 14,
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.clkrc = 0x03, .com4 = 0x41, .dm_lnl = 0x1a },
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{ .input_clk = 26000000, .framerate = 30,
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.clkrc = 0x01, .com4 = 0x41, .dm_lnl = 0x2b },
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{ .input_clk = 26000000, .framerate = 15,
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.clkrc = 0x03, .com4 = 0x41, .dm_lnl = 0x2b },
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{ .input_clk = 26000000, .framerate = 25,
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.clkrc = 0x01, .com4 = 0x41, .dm_lnl = 0x99 },
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{ .input_clk = 26000000, .framerate = 14,
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.clkrc = 0x03, .com4 = 0x41, .dm_lnl = 0x46 },
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{ .input_clk = 13000000, .framerate = 30,
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.clkrc = 0x00, .com4 = 0x41, .dm_lnl = 0x2b },
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{ .input_clk = 13000000, .framerate = 15,
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.clkrc = 0x01, .com4 = 0x41, .dm_lnl = 0x2b },
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{ .input_clk = 13000000, .framerate = 25,
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.clkrc = 0x00, .com4 = 0x41, .dm_lnl = 0x99 },
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{ .input_clk = 13000000, .framerate = 14,
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.clkrc = 0x01, .com4 = 0x41, .dm_lnl = 0x46 },
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};
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static const struct ov7725_pixel_format ov7725_pf_configs[] = {
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{ .pixel_format = VIDEO_PIX_FMT_RGB565, .com7 = (1 << 2) | (2) }
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};
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static const struct ov7725_reg ov7725_init_reg_tb[] = {
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/*Output config*/
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{ OV7725_CLKRC, 0x00 },
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{ OV7725_COM7, 0x06 },
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{ OV7725_HSTART, 0x3f },
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{ OV7725_HSIZE, 0x50 },
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{ OV7725_VSTART, 0x03 },
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{ OV7725_VSIZE, 0x78 },
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{ OV7725_HREF, 0x00 },
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{ OV7725_HOUTSIZE, 0x50 },
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{ OV7725_VOUTSIZE, 0x78 },
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/*DSP control*/
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{ OV7725_TGT_B, 0x7f },
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{ OV7725_FIXGAIN, 0x09 },
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{ OV7725_AWB_CTRL0, 0xe0 },
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{ OV7725_DSP_CTRL1, 0xff },
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{ OV7725_DSP_CTRL2, 0x00 },
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{ OV7725_DSP_CTRL3, 0x00 },
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{ OV7725_DSP_CTRL4, 0x00 },
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/*AGC AEC AWB*/
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{ OV7725_COM8, 0xf0 },
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{ OV7725_COM4, 0x81 },
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{ OV7725_COM6, 0xc5 },
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{ OV7725_COM9, 0x11 },
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{ OV7725_BDBASE, 0x7F },
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{ OV7725_BDMSTEP, 0x03 },
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{ OV7725_AEW, 0x40 },
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{ OV7725_AEB, 0x30 },
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{ OV7725_VPT, 0xa1 },
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{ OV7725_EXHCL, 0x9e },
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{ OV7725_AWB_CTRL3, 0xaa },
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{ OV7725_COM8, 0xff },
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/*matrix shapness brightness contrast*/
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{ OV7725_EDGE1, 0x08 },
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{ OV7725_DNSOFF, 0x01 },
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{ OV7725_EDGE2, 0x03 },
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{ OV7725_EDGE3, 0x00 },
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{ OV7725_MTX1, 0xb0 },
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{ OV7725_MTX2, 0x9d },
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{ OV7725_MTX3, 0x13 },
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{ OV7725_MTX4, 0x16 },
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{ OV7725_MTX5, 0x7b },
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{ OV7725_MTX6, 0x91 },
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{ OV7725_MTX_CTRL, 0x1e },
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{ OV7725_BRIGHT, 0x08 },
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{ OV7725_CNST, 0x20 },
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{ OV7725_UVADJ0, 0x81 },
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{ OV7725_SDE, 0X06 },
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{ OV7725_USAT, 0x65 },
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{ OV7725_VSAT, 0x65 },
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{ OV7725_HUECOS, 0X80 },
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{ OV7725_HUESIN, 0X80 },
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/*GAMMA config*/
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{ OV7725_GAM1, 0x0c },
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{ OV7725_GAM2, 0x16 },
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{ OV7725_GAM3, 0x2a },
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{ OV7725_GAM4, 0x4e },
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{ OV7725_GAM5, 0x61 },
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{ OV7725_GAM6, 0x6f },
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{ OV7725_GAM7, 0x7b },
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{ OV7725_GAM8, 0x86 },
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{ OV7725_GAM9, 0x8e },
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{ OV7725_GAM10, 0x97 },
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{ OV7725_GAM11, 0xa4 },
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{ OV7725_GAM12, 0xaf },
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{ OV7725_GAM13, 0xc5 },
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{ OV7725_GAM14, 0xd7 },
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{ OV7725_GAM15, 0xe8 },
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{ OV7725_SLOP, 0x20 },
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{ OV7725_COM3, 0x40 },
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{ OV7725_COM5, 0xf5 },
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{ OV7725_COM10, 0x02 },
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{ OV7725_COM2, 0x01 }
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};
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static int ov7725_write_reg(const struct device *dev, uint8_t reg_addr,
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uint8_t value)
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{
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struct ov7725_data *drv_data = dev->data;
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struct i2c_msg msgs[2];
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msgs[0].buf = (uint8_t *)®_addr;
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msgs[0].len = 1;
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msgs[0].flags = I2C_MSG_WRITE;
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msgs[1].buf = (uint8_t *)&value;
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msgs[1].len = 1;
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msgs[1].flags = I2C_MSG_WRITE | I2C_MSG_STOP;
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return i2c_transfer(drv_data->i2c, msgs, 2, drv_data->i2c_addr);
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}
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static int ov7725_read_reg(const struct device *dev, uint8_t reg_addr,
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uint8_t *value)
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{
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struct ov7725_data *drv_data = dev->data;
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struct i2c_msg msgs[2];
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msgs[0].buf = (uint8_t *)®_addr;
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msgs[0].len = 1;
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/*
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* When using I2C to read the registers of the SCCB device,
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* a stop bit is required after writing the register address
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*/
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msgs[0].flags = I2C_MSG_WRITE | I2C_MSG_STOP;
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msgs[1].buf = (uint8_t *)value;
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msgs[1].len = 1;
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msgs[1].flags = I2C_MSG_READ | I2C_MSG_STOP | I2C_MSG_RESTART;
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return i2c_transfer(drv_data->i2c, msgs, 2, drv_data->i2c_addr);
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}
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int ov7725_modify_reg(const struct device *dev,
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uint8_t reg_addr,
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uint8_t clear_mask,
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uint8_t value)
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{
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int ret;
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uint8_t set_value;
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ret = ov7725_read_reg(dev, reg_addr, &set_value);
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if (ret == 0) {
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set_value = (set_value & (~clear_mask)) |
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(set_value & clear_mask);
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ret = ov7725_write_reg(dev, reg_addr, set_value);
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}
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return ret;
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}
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static int ov7725_write_all(const struct device *dev,
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const struct ov7725_reg *regs,
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uint16_t reg_num)
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{
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uint16_t i = 0;
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for (i = 0; i < reg_num; i++) {
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int err;
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err = ov7725_write_reg(dev, regs[i].addr, regs[i].value);
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if (err) {
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return err;
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}
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}
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return 0;
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}
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static int ov7725_set_clock(const struct device *dev,
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unsigned int framerate,
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unsigned int input_clk)
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{
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for (unsigned int i = 0; i < ARRAY_SIZE(ov7725_clock_configs); i++) {
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if ((ov7725_clock_configs[i].framerate == framerate) &&
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(ov7725_clock_configs[i].input_clk == input_clk)) {
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ov7725_write_reg(dev, OV7725_CLKRC,
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ov7725_clock_configs[i].clkrc);
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ov7725_modify_reg(dev, OV7725_COM4, 0xc0,
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ov7725_clock_configs[i].com4);
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ov7725_write_reg(dev, OV7725_EXHCL, 0x00);
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ov7725_write_reg(dev, OV7725_DM_LNL,
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ov7725_clock_configs[i].dm_lnl);
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ov7725_write_reg(dev, OV7725_DM_LNH, 0x00);
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ov7725_write_reg(dev, OV7725_ADVFL, 0x00);
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ov7725_write_reg(dev, OV7725_ADVFH, 0x00);
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return ov7725_write_reg(dev, OV7725_COM5, 0x65);
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}
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}
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return -1;
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}
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static int ov7725_set_fmt(const struct device *dev,
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enum video_endpoint_id ep,
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struct video_format *fmt)
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{
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struct ov7725_data *drv_data = dev->data;
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uint8_t com10 = 0;
|
|
uint16_t width, height;
|
|
uint16_t hstart, vstart, hsize;
|
|
int ret;
|
|
|
|
/* we only support one format for now (VGA RGB565) */
|
|
if (fmt->pixelformat != VIDEO_PIX_FMT_RGB565 || fmt->height != 480 ||
|
|
fmt->width != 640) {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
width = fmt->width;
|
|
height = fmt->height;
|
|
|
|
if (!memcmp(&drv_data->fmt, fmt, sizeof(drv_data->fmt))) {
|
|
/* nothing to do */
|
|
return 0;
|
|
}
|
|
|
|
drv_data->fmt = *fmt;
|
|
|
|
/* Configure Sensor */
|
|
ret = ov7725_write_all(dev, ov7725_init_reg_tb,
|
|
ARRAY_SIZE(ov7725_init_reg_tb));
|
|
if (ret) {
|
|
LOG_ERR("Unable to write ov7725 config");
|
|
return ret;
|
|
}
|
|
|
|
/* Set clock : framerate 30fps, input clock 24M*/
|
|
ov7725_set_clock(dev, 30, 24000000);
|
|
|
|
/* Set output format */
|
|
for (uint8_t i = 0; i < ARRAY_SIZE(ov7725_pf_configs); i++) {
|
|
if (ov7725_pf_configs[i].pixel_format == fmt->pixelformat) {
|
|
ret = ov7725_modify_reg(dev,
|
|
OV7725_COM7,
|
|
0x1FU,
|
|
ov7725_pf_configs[i].com7);
|
|
if (ret) {
|
|
LOG_ERR("Unable to write ov7725 pixel format");
|
|
return ret;
|
|
}
|
|
}
|
|
}
|
|
|
|
ov7725_modify_reg(dev, OV7725_COM7, (1 << 5), (0 << 5));
|
|
|
|
com10 |= OV7725_COM10_VSYNC_NEG_MASK;
|
|
ov7725_write_reg(dev, OV7725_COM10, com10);
|
|
|
|
/* Don't swap output MSB/LSB. */
|
|
ov7725_write_reg(dev, OV7725_COM3, 0x00);
|
|
|
|
/*
|
|
* Output drive capability
|
|
* 0: 1X
|
|
* 1: 2X
|
|
* 2: 3X
|
|
* 3: 4X
|
|
*/
|
|
ov7725_modify_reg(dev, OV7725_COM2, 0x03, 0x03);
|
|
|
|
/* Resolution and timing. */
|
|
hstart = 0x22U << 2U;
|
|
vstart = 0x07U << 1U;
|
|
hsize = width + 16U;
|
|
|
|
/* Set the window size. */
|
|
ov7725_write_reg(dev, OV7725_HSTART, hstart >> 2U);
|
|
ov7725_write_reg(dev, OV7725_HSIZE, hsize >> 2U);
|
|
ov7725_write_reg(dev, OV7725_VSTART, vstart >> 1U);
|
|
ov7725_write_reg(dev, OV7725_VSIZE, height >> 1U);
|
|
ov7725_write_reg(dev, OV7725_HOUTSIZE, width >> 2U);
|
|
ov7725_write_reg(dev, OV7725_VOUTSIZE, height >> 1U);
|
|
ov7725_write_reg(dev, OV7725_HREF,
|
|
((vstart & 1U) << 6U) |
|
|
((hstart & 3U) << 4U) |
|
|
((height & 1U) << 2U) |
|
|
((hsize & 3U) << 0U));
|
|
return ov7725_write_reg(dev, OV7725_EXHCH,
|
|
((height & 1U) << 2U) |
|
|
((width & 3U) << 0U));
|
|
}
|
|
|
|
static int ov7725_get_fmt(const struct device *dev,
|
|
enum video_endpoint_id ep,
|
|
struct video_format *fmt)
|
|
{
|
|
struct ov7725_data *drv_data = dev->data;
|
|
|
|
*fmt = drv_data->fmt;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ov7725_stream_start(const struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int ov7725_stream_stop(const struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct video_format_cap fmts[] = {
|
|
{
|
|
.pixelformat = VIDEO_PIX_FMT_RGB565,
|
|
.width_min = 640,
|
|
.width_max = 640,
|
|
.height_min = 480,
|
|
.height_max = 480,
|
|
.width_step = 0,
|
|
.height_step = 0,
|
|
},
|
|
{ 0 }
|
|
};
|
|
|
|
static int ov7725_get_caps(const struct device *dev,
|
|
enum video_endpoint_id ep,
|
|
struct video_caps *caps)
|
|
{
|
|
caps->format_caps = fmts;
|
|
return 0;
|
|
}
|
|
|
|
static const struct video_driver_api ov7725_driver_api = {
|
|
.set_format = ov7725_set_fmt,
|
|
.get_format = ov7725_get_fmt,
|
|
.get_caps = ov7725_get_caps,
|
|
.stream_start = ov7725_stream_start,
|
|
.stream_stop = ov7725_stream_stop,
|
|
};
|
|
|
|
static int ov7725_init(const struct device *dev)
|
|
{
|
|
struct ov7725_data *drv_data = dev->data;
|
|
struct video_format fmt;
|
|
uint8_t pid, ver;
|
|
int ret;
|
|
|
|
|
|
if (drv_data->reset_gpio) {
|
|
ret = gpio_pin_configure(drv_data->reset_gpio,
|
|
drv_data->reset_pin,
|
|
GPIO_OUTPUT_ACTIVE |
|
|
drv_data->reset_flags);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
gpio_pin_set(drv_data->reset_gpio,
|
|
drv_data->reset_pin,
|
|
0);
|
|
k_sleep(K_MSEC(1));
|
|
gpio_pin_set(drv_data->reset_gpio,
|
|
drv_data->reset_pin,
|
|
1);
|
|
k_sleep(K_MSEC(1));
|
|
}
|
|
|
|
/* Identify the device. */
|
|
ret = ov7725_read_reg(dev, OV7725_PID, &pid);
|
|
if (ret) {
|
|
LOG_ERR("Unable to read PID");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = ov7725_read_reg(dev, OV7725_VER, &ver);
|
|
if (ret) {
|
|
LOG_ERR("Unable to read VER");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (OV7725_REVISION != (((uint32_t)pid << 8U) | (uint32_t)ver)) {
|
|
LOG_ERR("OV7725 Get Vision fail\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Device identify OK, perform software reset. */
|
|
ov7725_write_reg(dev, OV7725_COM7, 0x80);
|
|
|
|
k_sleep(K_MSEC(2));
|
|
|
|
/* set default/init format VGA RGB565 */
|
|
fmt.pixelformat = VIDEO_PIX_FMT_RGB565;
|
|
fmt.width = 640;
|
|
fmt.height = 480;
|
|
fmt.pitch = 640 * 2;
|
|
ret = ov7725_set_fmt(dev, VIDEO_EP_OUT, &fmt);
|
|
if (ret) {
|
|
LOG_ERR("Unable to configure default format");
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Unique Instance */
|
|
static struct ov7725_data ov7725_data_0;
|
|
|
|
static int ov7725_init_0(const struct device *dev)
|
|
{
|
|
struct ov7725_data *drv_data = dev->data;
|
|
char *gpio_name = DT_INST_GPIO_LABEL(0, reset_gpios);
|
|
|
|
drv_data->reset_pin = DT_INST_GPIO_PIN(0, reset_gpios),
|
|
drv_data->reset_flags = DT_INST_GPIO_FLAGS(0, reset_gpios),
|
|
|
|
drv_data->i2c = device_get_binding(DT_INST_BUS_LABEL(0));
|
|
if (drv_data->i2c == NULL) {
|
|
LOG_ERR("Failed to get pointer to %s device!",
|
|
DT_INST_LABEL(0));
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (gpio_name) {
|
|
drv_data->reset_gpio = device_get_binding(gpio_name);
|
|
if (drv_data->reset_gpio == NULL) {
|
|
LOG_ERR("Failed to get pointer to %s device!",
|
|
gpio_name);
|
|
}
|
|
}
|
|
|
|
drv_data->i2c_addr = DT_INST_REG_ADDR(0);
|
|
|
|
return ov7725_init(dev);
|
|
}
|
|
|
|
DEVICE_DT_INST_DEFINE(0, &ov7725_init_0, device_pm_control_nop,
|
|
&ov7725_data_0, NULL,
|
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
|
&ov7725_driver_api);
|