137 lines
5.0 KiB
Plaintext
137 lines
5.0 KiB
Plaintext
# Copyright (c) 2024 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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#
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menu "SMP Options"
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config SMP
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bool "Symmetric multiprocessing support"
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depends on USE_SWITCH
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depends on !ATOMIC_OPERATIONS_C
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help
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When true, kernel will be built with SMP support, allowing
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more than one CPU to schedule Zephyr tasks at a time.
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config USE_SWITCH
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bool "Use new-style _arch_switch instead of arch_swap"
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depends on USE_SWITCH_SUPPORTED
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help
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The _arch_switch() API is a lower level context switching
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primitive than the original arch_swap mechanism. It is required
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for an SMP-aware scheduler, or if the architecture does not
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provide arch_swap. In uniprocess situations where the
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architecture provides both, _arch_switch incurs more somewhat
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overhead and may be slower.
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config USE_SWITCH_SUPPORTED
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bool
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help
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Indicates whether _arch_switch() API is supported by the
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currently enabled platform. This option should be selected by
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platforms that implement it.
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config SMP_BOOT_DELAY
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bool "Delay booting secondary cores"
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depends on SMP
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help
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By default Zephyr will boot all available CPUs during start up.
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Select this option to skip this and allow custom code
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(architecture/SoC/board/application) to boot secondary CPUs at
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a later time.
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config MP_NUM_CPUS
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int "Number of CPUs/cores [DEPRECATED]"
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default MP_MAX_NUM_CPUS
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range 1 12
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help
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This is deprecated, please use MP_MAX_NUM_CPUS instead.
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config MP_MAX_NUM_CPUS
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int "Maximum number of CPUs/cores"
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default 1
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range 1 12
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help
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Maximum number of multiprocessing-capable cores available to the
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multicpu API and SMP features.
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config SCHED_IPI_SUPPORTED
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bool
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help
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True if the architecture supports a call to arch_sched_broadcast_ipi()
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to broadcast an interrupt that will call z_sched_ipi() on other CPUs
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in the system. Required for k_thread_abort() to operate with
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reasonable latency (otherwise we might have to wait for the other
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thread to take an interrupt, which can be arbitrarily far in the
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future).
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config SCHED_IPI_CASCADE
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bool "Use cascading IPIs to correct localized scheduling"
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depends on SCHED_CPU_MASK && !SCHED_CPU_MASK_PIN_ONLY
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default n
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help
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Threads that are preempted by a local thread (a thread that is
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restricted by its CPU mask to execute on a subset of all CPUs) may
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trigger additional IPIs when the preempted thread is of higher
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priority than a currently executing thread on another CPU. Although
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these cascading IPIs will ensure that the system will settle upon a
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valid set of high priority threads, it comes at a performance cost.
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config TRACE_SCHED_IPI
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bool "Test IPI"
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help
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When true, it will add a hook into z_sched_ipi(), in order
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to check if schedule IPI has called or not, for testing
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purpose.
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depends on SCHED_IPI_SUPPORTED
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depends on MP_MAX_NUM_CPUS>1
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config IPI_OPTIMIZE
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bool "Optimize IPI delivery"
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default n
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depends on SCHED_IPI_SUPPORTED && MP_MAX_NUM_CPUS>1
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help
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When selected, the kernel will attempt to determine the minimum
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set of CPUs that need an IPI to trigger a reschedule in response to
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a thread newly made ready for execution. This increases the
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computation required at every scheduler operation by a value that is
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O(N) in the number of CPUs, and in exchange reduces the number of
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interrupts delivered. Which to choose is going to depend on
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application behavior. If the architecture also supports directing
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IPIs to specific CPUs then this has the potential to signficantly
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reduce the number of IPIs (and consequently ISRs) processed by the
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system as the number of CPUs increases. If not, the only benefit
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would be to not issue any IPIs if the newly readied thread is of
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lower priority than all the threads currently executing on other CPUs.
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config KERNEL_COHERENCE
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bool "Place all shared data into coherent memory"
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depends on ARCH_HAS_COHERENCE
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default y if SMP && MP_MAX_NUM_CPUS > 1
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select THREAD_STACK_INFO
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help
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When available and selected, the kernel will build in a mode
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where all shared data is placed in multiprocessor-coherent
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(generally "uncached") memory. Thread stacks will remain
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cached, as will application memory declared with
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__incoherent. This is intended for Zephyr SMP kernels
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running on cache-incoherent architectures only. Note that
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when this is selected, there is an implicit API change that
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assumes cache coherence to any memory passed to the kernel.
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Code that creates kernel data structures in uncached regions
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may fail strangely. Some assertions exist to catch these
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mistakes, but not all circumstances can be tested.
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config TICKET_SPINLOCKS
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bool "Ticket spinlocks for lock acquisition fairness [EXPERIMENTAL]"
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select EXPERIMENTAL
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help
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Basic spinlock implementation is based on single
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atomic variable and doesn't guarantee locking fairness
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across multiple CPUs. It's even possible that single CPU
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will win the contention every time which will result
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in a live-lock.
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Ticket spinlocks provide a FIFO order of lock acquisition
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which resolves such unfairness issue at the cost of slightly
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increased memory footprint.
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endmenu
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