zephyr/soc/xtensa
Pavlo Hamov f9ab7d12e2 soc: esp32s2: Fix RAM offset calculation
Depending on cache setting RAM start must be adjusted.
Fix offset selection

Signed-off-by: Pavlo Hamov <p.hamov@venstar.com>
2021-10-13 10:13:58 -04:00
..
esp32 soc: esp32: partial code standardization 2021-10-10 14:52:41 -04:00
esp32s2 soc: esp32s2: Fix RAM offset calculation 2021-10-13 10:13:58 -04:00
intel_adsp Revert "linker: xtensa: move IDT_LIST region" 2021-09-08 20:29:53 -05:00
intel_s1000 Revert "linker: xtensa: move IDT_LIST region" 2021-09-08 20:29:53 -05:00
nxp_adsp arch: xtensa: modify asm for interrupt sections 2021-08-28 23:27:02 -04:00
sample_controller linker: align _image_text_start/end/size linker symbols name 2021-08-28 08:48:03 -04:00
CMakeLists.txt