171 lines
3.4 KiB
ArmAsm
171 lines
3.4 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Reset handler
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*
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* Reset handler that prepares the system for running C code.
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include <swap_macros.h>
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GDATA(_interrupt_stack)
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GDATA(z_main_stack)
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GDATA(_VectorTable)
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/* use one of the available interrupt stacks during init */
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#define INIT_STACK _interrupt_stack
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#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
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GTEXT(__reset)
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GTEXT(__start)
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/**
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*
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* @brief Reset vector
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*
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* Ran when the system comes out of reset. The processor is at supervisor level.
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*
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* Locking interrupts prevents anything from interrupting the CPU.
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*
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* When these steps are completed, jump to _PrepC(), which will finish setting
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* up the system for running C code.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT,__reset)
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SECTION_FUNC(TEXT,__start)
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/* lock interrupts: will get unlocked when switch to main task
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* also make sure the processor in the correct status
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*/
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mov_s r0, 0
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kflag r0
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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sflag r0
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#endif
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#if defined(CONFIG_BOOT_TIME_MEASUREMENT) && defined(CONFIG_ARCV2_TIMER)
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/*
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* ARCV2 timer (timer0) is a free run timer, let it start to count
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* here.
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*/
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mov_s r0, 0xffffffff
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sr r0, [_ARC_V2_TMR0_LIMIT]
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mov_s r0, 0
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sr r0, [_ARC_V2_TMR0_COUNT]
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#endif
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/* interrupt related init */
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#ifndef CONFIG_ARC_NORMAL_FIRMWARE
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/* IRQ_ACT and IRQ_CTRL should be initialized and set in secure mode */
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sr r0, [_ARC_V2_AUX_IRQ_ACT]
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sr r0, [_ARC_V2_AUX_IRQ_CTRL]
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#endif
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sr r0, [_ARC_V2_AUX_IRQ_HINT]
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/* set the vector table base early,
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* so that exception vectors can be handled.
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*/
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mov_s r0, _VectorTable
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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sr r0, [_ARC_V2_IRQ_VECT_BASE_S]
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#else
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sr r0, [_ARC_V2_IRQ_VECT_BASE]
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#endif
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#if defined(CONFIG_USERSPACE)
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lr r0, [_ARC_V2_STATUS32]
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bset r0, r0, _ARC_V2_STATUS32_US_BIT
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kflag r0
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#endif
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#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
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lr r0, [_ARC_V2_STATUS32]
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bset r0, r0, _ARC_V2_STATUS32_AD_BIT
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kflag r0
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#endif
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mov_s r1, 1
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invalidate_and_disable_icache:
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lr r0, [_ARC_V2_I_CACHE_BUILD]
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and.f r0, r0, 0xff
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bz.nd invalidate_dcache
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mov_s r2, 0
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sr r2, [_ARC_V2_IC_IVIC]
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/* writing to IC_IVIC needs 3 NOPs */
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nop_s
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nop_s
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nop_s
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sr r1, [_ARC_V2_IC_CTRL]
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invalidate_dcache:
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lr r3, [_ARC_V2_D_CACHE_BUILD]
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and.f r3, r3, 0xff
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bz.nd done_cache_invalidate
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sr r1, [_ARC_V2_DC_IVDC]
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done_cache_invalidate:
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#if defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES) && \
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!defined(CONFIG_BOOTLOADER_CONTEXT_RESTORE)
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jl @_sys_resume_from_deep_sleep
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#endif
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#ifdef CONFIG_SMP
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_get_cpu_id r0
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breq r0, 0, _master_core_startup
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/*
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* Non-masters wait for master core (core 0) to boot enough
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*/
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_slave_core_wait:
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ld r1, [arc_cpu_wake_flag]
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brne r0, r1, _slave_core_wait
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/* signal master core that slave core runs */
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st 0, [arc_cpu_wake_flag]
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/* get sp set by master core */
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_get_curr_cpu_irq_stack sp
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j z_arch_slave_start
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_master_core_startup:
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#endif
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#ifdef CONFIG_INIT_STACKS
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/*
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* use the main stack to call memset on the interrupt stack and the
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* FIRQ stack when CONFIG_INIT_STACKS is enabled before switching to
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* one of them for the rest of the early boot
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*/
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mov_s sp, z_main_stack
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add sp, sp, CONFIG_MAIN_STACK_SIZE
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mov_s r0, _interrupt_stack
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mov_s r1, 0xaa
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mov_s r2, CONFIG_ISR_STACK_SIZE
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jl memset
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#endif /* CONFIG_INIT_STACKS */
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mov_s sp, INIT_STACK
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add sp, sp, INIT_STACK_SIZE
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j @_PrepC
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