zephyr/soc/arm/nordic_nrf/nrf52/soc.c

93 lines
1.8 KiB
C

/*
* Copyright (c) 2016 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Nordic Semiconductor nRF52 family processor
*
* This module provides routines to initialize and support board-level hardware
* for the Nordic Semiconductor nRF52 family processor.
*/
#include <kernel.h>
#include <init.h>
#include <cortex_m/exc.h>
#include <nrfx.h>
#include <nrf_power.h>
#include <soc/nrfx_coredep.h>
#include <logging/log.h>
#ifdef CONFIG_RUNTIME_NMI
extern void z_NmiInit(void);
#define NMI_INIT() z_NmiInit()
#else
#define NMI_INIT()
#endif
#if defined(CONFIG_SOC_NRF52810)
#include <system_nrf52810.h>
#elif defined(CONFIG_SOC_NRF52811)
#include <system_nrf52811.h>
#elif defined(CONFIG_SOC_NRF52832)
#include <system_nrf52.h>
#elif defined(CONFIG_SOC_NRF52840)
#include <system_nrf52840.h>
#else
#error "Unknown SoC."
#endif
#include <hal/nrf_power.h>
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
LOG_MODULE_REGISTER(soc);
/* Overrides the weak ARM implementation:
Set general purpose retention register and reboot */
void sys_arch_reboot(int type)
{
nrf_power_gpregret_set((uint8_t)type);
NVIC_SystemReset();
}
static int nordicsemi_nrf52_init(struct device *arg)
{
u32_t key;
ARG_UNUSED(arg);
key = irq_lock();
#ifdef CONFIG_NRF_ENABLE_ICACHE
/* Enable the instruction cache */
NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
#endif
#if defined(CONFIG_SOC_DCDC_NRF52X)
nrf_power_dcdcen_set(true);
#endif
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
irq_unlock(key);
return 0;
}
void z_arch_busy_wait(u32_t time_us)
{
nrfx_coredep_delay_us(time_us);
}
void z_platform_init(void)
{
SystemInit();
}
SYS_INIT(nordicsemi_nrf52_init, PRE_KERNEL_1, 0);