98 lines
1.9 KiB
Plaintext
98 lines
1.9 KiB
Plaintext
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/xtensa.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cadence,tensilica-xtensa-lx4";
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reg = <0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "cadence,tensilica-xtensa-lx4";
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reg = <1>;
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};
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};
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sram0: memory@be000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xbe000000 DT_SIZE_K(512)>;
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};
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sram1: memory@be800000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xbe800000 DT_SIZE_K(128)>;
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};
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soc {
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core_intc: core_intc@0 {
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compatible = "xtensa,core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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cavs0: cavs@1600 {
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compatible = "intel,cavs-intc";
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reg = <0x1600 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <6 0 0>;
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interrupt-parent = <&core_intc>;
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label = "CAVS_0";
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};
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cavs1: cavs@1610 {
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compatible = "intel,cavs-intc";
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reg = <0x1610 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0xA 0 0>;
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interrupt-parent = <&core_intc>;
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label = "CAVS_1";
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};
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cavs2: cavs@1620 {
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compatible = "intel,cavs-intc";
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reg = <0x1620 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0XD 0 0>;
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interrupt-parent = <&core_intc>;
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label = "CAVS_2";
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};
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cavs3: cavs@1630 {
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compatible = "intel,cavs-intc";
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reg = <0x1630 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0x10 0 0>;
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interrupt-parent = <&core_intc>;
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label = "CAVS_3";
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};
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idc: idc@1200 {
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compatible = "intel,cavs-idc";
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label = "CAVS_IDC";
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reg = <0x1200 0x80>;
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interrupts = <8 0 0>;
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interrupt-parent = <&cavs0>;
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};
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};
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};
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