429 lines
11 KiB
C
429 lines
11 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT snps_designware_dma
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#include <errno.h>
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#include <stdio.h>
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#include <string.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <drivers/dma.h>
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#include <soc.h>
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#include "dma_dw.h"
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#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(dma_dw);
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#define BYTE (1)
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#define WORD (2)
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#define DWORD (4)
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/* CFG_LO */
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#define DW_CFG_CLASS(x) (x << 29)
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/* CFG_HI */
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#define DW_CFGH_SRC_PER(x) ((x & 0xf) | ((x & 0x30) << 24))
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#define DW_CFGH_DST_PER(x) (((x & 0xf) << 4) | ((x & 0x30) << 26))
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/* default initial setup register values */
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#define DW_CFG_LOW_DEF 0x0
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#define DEV_NAME(dev) ((dev)->name)
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#define DEV_DATA(dev) ((struct dw_dma_dev_data *const)(dev)->driver_data)
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#define DEV_CFG(dev) \
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((const struct dw_dma_dev_cfg *const)(dev)->config_info)
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/* number of tries to wait for reset */
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#define DW_DMA_CFG_TRIES 10000
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#define INT_MASK_ALL 0xFF00
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static ALWAYS_INLINE void dw_write(uint32_t dma_base, uint32_t reg, uint32_t value)
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{
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*((volatile uint32_t*)(dma_base + reg)) = value;
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}
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static ALWAYS_INLINE uint32_t dw_read(uint32_t dma_base, uint32_t reg)
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{
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return *((volatile uint32_t*)(dma_base + reg));
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}
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static void dw_dma_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct dw_dma_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct dw_dma_dev_data *const dev_data = DEV_DATA(dev);
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struct dma_chan_data *chan_data;
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uint32_t status_tfr = 0U;
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uint32_t status_block = 0U;
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uint32_t status_err = 0U;
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uint32_t status_intr;
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uint32_t channel;
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status_intr = dw_read(dev_cfg->base, DW_INTR_STATUS);
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if (!status_intr) {
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LOG_ERR("status_intr = %d", status_intr);
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}
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/* get the source of our IRQ. */
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status_block = dw_read(dev_cfg->base, DW_STATUS_BLOCK);
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status_tfr = dw_read(dev_cfg->base, DW_STATUS_TFR);
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/* TODO: handle errors, just clear them atm */
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status_err = dw_read(dev_cfg->base, DW_STATUS_ERR);
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if (status_err) {
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LOG_ERR("status_err = %d\n", status_err);
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dw_write(dev_cfg->base, DW_CLEAR_ERR, status_err);
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}
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/* clear interrupts */
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dw_write(dev_cfg->base, DW_CLEAR_BLOCK, status_block);
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dw_write(dev_cfg->base, DW_CLEAR_TFR, status_tfr);
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/* Dispatch callbacks for channels depending upon the bit set */
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while (status_block) {
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channel = find_lsb_set(status_block) - 1;
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status_block &= ~(1 << channel);
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chan_data = &dev_data->chan[channel];
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if (chan_data->dma_blkcallback) {
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/* Ensure the linked list (chan_data->lli) is
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* freed in the user callback function once
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* all the blocks are transferred.
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*/
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chan_data->dma_blkcallback(chan_data->blkcallback_arg,
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channel, 0);
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}
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}
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while (status_tfr) {
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channel = find_lsb_set(status_tfr) - 1;
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status_tfr &= ~(1 << channel);
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chan_data = &dev_data->chan[channel];
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if (chan_data->dma_tfrcallback) {
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chan_data->dma_tfrcallback(chan_data->tfrcallback_arg,
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channel, 0);
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}
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}
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}
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static int dw_dma_config(struct device *dev, uint32_t channel,
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struct dma_config *cfg)
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{
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struct dw_dma_dev_data *const dev_data = DEV_DATA(dev);
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const struct dw_dma_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct dma_chan_data *chan_data;
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struct dma_block_config *cfg_blocks;
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uint32_t m_size;
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uint32_t tr_width;
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uint32_t ctrl_lo;
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if (channel >= DW_MAX_CHAN) {
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return -EINVAL;
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}
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__ASSERT_NO_MSG(cfg->source_data_size == cfg->dest_data_size);
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__ASSERT_NO_MSG(cfg->source_burst_length == cfg->dest_burst_length);
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if (cfg->source_data_size != BYTE && cfg->source_data_size != WORD &&
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cfg->source_data_size != DWORD) {
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LOG_ERR("Invalid 'source_data_size' value");
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return -EINVAL;
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}
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cfg_blocks = cfg->head_block;
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if ((cfg_blocks->next_block) || (cfg->block_count > 1)) {
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/*
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* return error since the application may have allocated
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* memory for the buffers that may be lost when the DMA
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* driver discards the buffers provided in the linked blocks
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*/
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LOG_ERR("block_count > 1 not supported");
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return -EINVAL;
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}
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chan_data = &dev_data->chan[channel];
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/* default channel config */
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chan_data->direction = cfg->channel_direction;
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/* data_size = (2 ^ tr_width) */
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tr_width = find_msb_set(cfg->source_data_size) - 1;
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LOG_DBG("Ch%u: tr_width=%d", channel, tr_width);
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/* burst_size = (2 ^ msize) */
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m_size = find_msb_set(cfg->source_burst_length) - 1;
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LOG_DBG("Ch%u: m_size=%d", channel, m_size);
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ctrl_lo = DW_CTLL_SRC_WIDTH(tr_width) | DW_CTLL_DST_WIDTH(tr_width);
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ctrl_lo |= DW_CTLL_SRC_MSIZE(m_size) | DW_CTLL_DST_MSIZE(m_size);
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/* enable interrupt */
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ctrl_lo |= DW_CTLL_INT_EN;
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switch (cfg->channel_direction) {
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case MEMORY_TO_MEMORY:
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ctrl_lo |= DW_CTLL_FC_M2M;
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ctrl_lo |= DW_CTLL_SRC_INC | DW_CTLL_DST_INC;
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break;
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case MEMORY_TO_PERIPHERAL:
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ctrl_lo |= DW_CTLL_FC_M2P;
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ctrl_lo |= DW_CTLL_SRC_INC | DW_CTLL_DST_FIX;
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/* Assign a hardware handshaking interface (0-15) to the
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* destination of channel
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*/
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dw_write(dev_cfg->base, DW_CFG_HIGH(channel),
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DW_CFGH_DST_PER(cfg->dma_slot));
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break;
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case PERIPHERAL_TO_MEMORY:
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ctrl_lo |= DW_CTLL_FC_P2M;
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ctrl_lo |= DW_CTLL_SRC_FIX | DW_CTLL_DST_INC;
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/* Assign a hardware handshaking interface (0-15) to the
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* source of channel
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*/
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dw_write(dev_cfg->base, DW_CFG_HIGH(channel),
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DW_CFGH_SRC_PER(cfg->dma_slot));
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break;
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default:
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LOG_ERR("channel_direction %d is not supported",
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cfg->channel_direction);
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return -EINVAL;
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}
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/* channel needs started from scratch, so write SARn, DARn */
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dw_write(dev_cfg->base, DW_SAR(channel), cfg_blocks->source_address);
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dw_write(dev_cfg->base, DW_DAR(channel), cfg_blocks->dest_address);
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/* Configure a callback appropriately depending on whether the
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* interrupt is requested at the end of transaction completion or
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* at the end of each block.
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*/
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if (cfg->complete_callback_en) {
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chan_data->dma_blkcallback = cfg->dma_callback;
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chan_data->blkcallback_arg = cfg->callback_arg;
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dw_write(dev_cfg->base, DW_MASK_BLOCK, INT_UNMASK(channel));
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} else {
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chan_data->dma_tfrcallback = cfg->dma_callback;
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chan_data->tfrcallback_arg = cfg->callback_arg;
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dw_write(dev_cfg->base, DW_MASK_TFR, INT_UNMASK(channel));
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}
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dw_write(dev_cfg->base, DW_MASK_ERR, INT_UNMASK(channel));
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/* write interrupt clear registers for the channel
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* ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr
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*/
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dw_write(dev_cfg->base, DW_CLEAR_TFR, 0x1 << channel);
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dw_write(dev_cfg->base, DW_CLEAR_BLOCK, 0x1 << channel);
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dw_write(dev_cfg->base, DW_CLEAR_SRC_TRAN, 0x1 << channel);
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dw_write(dev_cfg->base, DW_CLEAR_DST_TRAN, 0x1 << channel);
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dw_write(dev_cfg->base, DW_CLEAR_ERR, 0x1 << channel);
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/* single transfer, must set zero */
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dw_write(dev_cfg->base, DW_LLP(channel), 0);
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/* program CTLn */
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dw_write(dev_cfg->base, DW_CTRL_LOW(channel), ctrl_lo);
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dw_write(dev_cfg->base, DW_CTRL_HIGH(channel),
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DW_CFG_CLASS(dev_data->channel_data->chan[channel].class) |
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cfg_blocks->block_size);
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/* write channel config */
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dw_write(dev_cfg->base, DW_CFG_LOW(channel), DW_CFG_LOW_DEF);
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return 0;
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}
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static int dw_dma_reload(struct device *dev, uint32_t channel,
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uint32_t src, uint32_t dst, size_t size)
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{
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struct dw_dma_dev_data *const dev_data = DEV_DATA(dev);
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const struct dw_dma_dev_cfg *const dev_cfg = DEV_CFG(dev);
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if (channel >= DW_MAX_CHAN) {
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return -EINVAL;
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}
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dw_write(dev_cfg->base, DW_SAR(channel), src);
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dw_write(dev_cfg->base, DW_DAR(channel), dst);
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dw_write(dev_cfg->base, DW_CTRL_HIGH(channel),
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DW_CFG_CLASS(dev_data->channel_data->chan[channel].class) |
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size);
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return 0;
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}
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static int dw_dma_transfer_start(struct device *dev, uint32_t channel)
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{
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const struct dw_dma_dev_cfg *const dev_cfg = DEV_CFG(dev);
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if (channel >= DW_MAX_CHAN) {
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return -EINVAL;
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}
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/* enable the channel */
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dw_write(dev_cfg->base, DW_DMA_CHAN_EN, CHAN_ENABLE(channel));
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return 0;
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}
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static int dw_dma_transfer_stop(struct device *dev, uint32_t channel)
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{
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const struct dw_dma_dev_cfg *const dev_cfg = DEV_CFG(dev);
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if (channel >= DW_MAX_CHAN) {
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return -EINVAL;
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}
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/* disable the channel */
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dw_write(dev_cfg->base, DW_DMA_CHAN_EN, CHAN_DISABLE(channel));
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return 0;
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}
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static void dw_dma_setup(struct device *dev)
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{
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const struct dw_dma_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct dw_dma_dev_data *const dev_data = DEV_DATA(dev);
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struct dw_drv_plat_data *dp = dev_data->channel_data;
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int i;
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/* we cannot config DMAC if DMAC has been already enabled by host */
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if (dw_read(dev_cfg->base, DW_DMA_CFG) != 0) {
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dw_write(dev_cfg->base, DW_DMA_CFG, 0x0);
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}
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/* now check that it's 0 */
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for (i = DW_DMA_CFG_TRIES; i > 0; i--) {
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if (dw_read(dev_cfg->base, DW_DMA_CFG) == 0) {
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goto found;
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}
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}
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LOG_ERR("DW_DMA_CFG is non-zero\n");
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return;
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found:
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for (i = 0; i < DW_MAX_CHAN; i++) {
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dw_read(dev_cfg->base, DW_DMA_CHAN_EN);
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}
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/* enable the DMA controller */
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dw_write(dev_cfg->base, DW_DMA_CFG, 1);
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/* mask all interrupts for all 8 channels */
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dw_write(dev_cfg->base, DW_MASK_TFR, INT_MASK_ALL);
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dw_write(dev_cfg->base, DW_MASK_BLOCK, INT_MASK_ALL);
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dw_write(dev_cfg->base, DW_MASK_SRC_TRAN, INT_MASK_ALL);
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dw_write(dev_cfg->base, DW_MASK_DST_TRAN, INT_MASK_ALL);
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dw_write(dev_cfg->base, DW_MASK_ERR, INT_MASK_ALL);
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/* set channel priorities */
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for (i = 0; i < DW_MAX_CHAN; i++) {
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dw_write(dev_cfg->base, DW_CTRL_HIGH(i),
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DW_CFG_CLASS(dp->chan[i].class));
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}
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}
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static int dw_dma_init(struct device *dev)
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{
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const struct dw_dma_dev_cfg *const dev_cfg = DEV_CFG(dev);
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/* Disable all channels and Channel interrupts */
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dw_dma_setup(dev);
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/* Configure interrupts */
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dev_cfg->irq_config();
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LOG_INF("Device %s initialized", DEV_NAME(dev));
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return 0;
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}
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static const struct dma_driver_api dw_dma_driver_api = {
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.config = dw_dma_config,
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.reload = dw_dma_reload,
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.start = dw_dma_transfer_start,
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.stop = dw_dma_transfer_stop,
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};
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#define DW_DMAC_INIT(inst) \
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\
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DEVICE_DECLARE(dw_dma##inst); \
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\
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static struct dw_drv_plat_data dmac##inst = { \
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.chan[0] = { \
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.class = 6, \
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.weight = 0, \
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}, \
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.chan[1] = { \
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.class = 6, \
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.weight = 0, \
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}, \
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.chan[2] = { \
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.class = 6, \
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.weight = 0, \
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}, \
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.chan[3] = { \
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.class = 6, \
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.weight = 0, \
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}, \
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.chan[4] = { \
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.class = 6, \
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.weight = 0, \
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}, \
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.chan[5] = { \
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.class = 6, \
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.weight = 0, \
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}, \
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.chan[6] = { \
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.class = 6, \
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.weight = 0, \
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}, \
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.chan[7] = { \
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.class = 6, \
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.weight = 0, \
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}, \
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}; \
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\
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static void dw_dma##inst##_irq_config(void); \
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\
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static const struct dw_dma_dev_cfg dw_dma##inst##_config = { \
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.base = DT_INST_REG_ADDR(inst), \
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.irq_config = dw_dma##inst##_irq_config \
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}; \
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\
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static struct dw_dma_dev_data dw_dma##inst##_data = { \
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.channel_data = &dmac##inst, \
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}; \
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\
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DEVICE_AND_API_INIT(dw_dma##inst, DT_INST_LABEL(inst), \
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&dw_dma_init, \
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&dw_dma##inst##_data, \
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&dw_dma##inst##_config, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&dw_dma_driver_api); \
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\
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static void dw_dma##inst##_irq_config(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(inst), \
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DT_INST_IRQ(inst, priority), dw_dma_isr, \
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DEVICE_GET(dw_dma##inst), \
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DT_INST_IRQ(inst, sense)); \
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irq_enable(DT_INST_IRQN(inst)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(DW_DMAC_INIT)
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