335 lines
11 KiB
C
335 lines
11 KiB
C
/*
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* Copyright (c) 2021, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/pm/pm.h>
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#include <fsl_dcdc.h>
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#include <fsl_gpc.h>
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#include <zephyr/dt-bindings/pm/imx_spc.h>
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#include "power.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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/*
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* NOTE: When multicore support in RT1170/1160 is properly implemented,
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* power saving will improve when both cores request a transition to a low
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* power mode
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*/
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#ifdef CONFIG_CPU_CORTEX_M7
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#define GPC_CPU_MODE_CTRL GPC_CPU_MODE_CTRL_0
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#elif CONFIG_CPU_CORTEX_M4
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#define GPC_CPU_MODE_CTRL GPC_CPU_MODE_CTRL_1
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#else
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#error "RT11xx power code supports M4 and M7 cores only"
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#endif
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/* Configure the set point mappings for Cortex M4 and M7 cores */
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static void gpc_set_core_mappings(void)
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{
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uint8_t i, j;
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uint32_t tmp;
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#ifdef CONFIG_CPU_CORTEX_M7
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uint8_t mapping[SET_POINT_COUNT][SET_POINT_COUNT] = CPU0_COMPATIBLE_SP_TABLE;
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#elif CONFIG_CPU_CORTEX_M4
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uint8_t mapping[SET_POINT_COUNT][SET_POINT_COUNT] = CPU1_COMPATIBLE_SP_TABLE;
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#else
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#error "RT11xx power code supports M4 and M7 cores only"
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#endif
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/* Cortex Set point mappings */
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for (i = 0; i < SET_POINT_COUNT; i++) {
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tmp = 0x0;
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for (j = 0; j < SET_POINT_COUNT; j++) {
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tmp |= mapping[i][j] << mapping[0][j];
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}
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GPC_CM_SetSetPointMapping(GPC_CPU_MODE_CTRL, mapping[i][0], tmp);
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}
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}
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/* Configure GPC transition steps to enabled */
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static void gpc_set_transition_flow(void)
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{
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gpc_tran_step_config_t step_cfg;
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step_cfg.enableStep = true;
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step_cfg.cntMode = kGPC_StepCounterDisableMode;
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/* Cortex M7 */
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_SleepSsar, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_SleepLpcg, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_SleepPll, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_SleepIso, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_SleepReset, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_SleepPower, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_WakeupPower, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_WakeupReset, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_WakeupIso, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_WakeupPll, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_WakeupLpcg, &step_cfg);
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GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
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kGPC_CM_WakeupSsar, &step_cfg);
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/* Enable all steps in flow of set point transition */
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_SsarSave, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_LpcgOff, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_GroupDown, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_RootDown, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_PllOff, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_IsoOn, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_ResetEarly, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_PowerOff, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_BiasOff, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_BandgapPllLdoOff, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_LdoPre, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_DcdcDown, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_DcdcUp, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_LdoPost, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_BandgapPllLdoOn, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_BiasOn, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_PowerOn, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_ResetLate, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_IsoOff, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_PllOn, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_RootUp, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_GroupUp, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_LpcgOn, &step_cfg);
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GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL,
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kGPC_SP_SsarRestore, &step_cfg);
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/* Enable all steps in standby transition */
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_LpcgIn, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_PllIn, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_BiasIn, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_PldoIn, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_BandgapIn, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_LdoIn, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_DcdcIn, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_PmicIn, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_PmicOut, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_DcdcOut, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_LdoOut, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_BandgapOut, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_PldoOut, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_BiasOut, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_PllOut, &step_cfg);
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GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL,
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kGPC_STBY_LpcgOut, &step_cfg);
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}
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static void gpc_configure_interrupts(void)
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{
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uint8_t i;
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uint32_t irq = DT_IRQN(DT_INST(0, nxp_gpt_hw_timer));
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/* Disable all GPC interrupt sources */
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for (i = 0; i < GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT; i++) {
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GPC_CPU_MODE_CTRL->CM_IRQ_WAKEUP_MASK[i] |= 0xFFFFFFFF;
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}
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/* Enable GPT interrupt source for GPC- this is system timer */
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GPC_CM_EnableIrqWakeup(GPC_CPU_MODE_CTRL, irq, true);
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}
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/* Initializes configuration for the GPC */
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static void gpc_init(void)
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{
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/* Setup GPC set point mappings */
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gpc_set_core_mappings();
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/* Setup GPC set point transition flow */
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gpc_set_transition_flow();
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/* Allow GPC to disable ROSC */
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GPC_SET_POINT_CTRL->SP_ROSC_CTRL = ~OSC_RC_16M_STBY_VAL;
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/* Setup GPC interrupts */
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gpc_configure_interrupts();
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}
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/* Initializes DCDC converter with power saving settings */
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static void dcdc_init(void)
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{
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dcdc_config_t dcdc_config;
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dcdc_setpoint_config_t dcdc_setpoint_config;
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dcdc_buck_mode_1P8_target_vol_t buck1_8_voltage[16] =
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DCDC_1P8_BUCK_MODE_CONFIGURATION_TABLE;
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dcdc_buck_mode_1P0_target_vol_t buck1_0_voltage[16] =
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DCDC_1P0_BUCK_MODE_CONFIGURATION_TABLE;
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dcdc_standby_mode_1P8_target_vol_t standby1_8_voltage[16] =
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DCDC_1P8_STANDBY_MODE_CONFIGURATION_TABLE;
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dcdc_standby_mode_1P0_target_vol_t standby1_0_voltage[16] =
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DCDC_1P0_STANDBY_MODE_CONFIGURATION_TABLE;
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DCDC_BootIntoDCM(DCDC);
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dcdc_setpoint_config.enableDCDCMap = DCDC_ONOFF_SP_VAL;
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dcdc_setpoint_config.enableDigLogicMap = DCDC_DIG_ONOFF_SP_VAL;
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dcdc_setpoint_config.lowpowerMap = DCDC_LP_MODE_SP_VAL;
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dcdc_setpoint_config.standbyMap = DCDC_ONOFF_STBY_VAL;
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dcdc_setpoint_config.standbyLowpowerMap = DCDC_LP_MODE_STBY_VAL;
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dcdc_setpoint_config.buckVDD1P8TargetVoltage = buck1_8_voltage;
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dcdc_setpoint_config.buckVDD1P0TargetVoltage = buck1_0_voltage;
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dcdc_setpoint_config.standbyVDD1P8TargetVoltage = standby1_8_voltage;
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dcdc_setpoint_config.standbyVDD1P0TargetVoltage = standby1_0_voltage;
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DCDC_SetPointInit(DCDC, &dcdc_setpoint_config);
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DCDC_GetDefaultConfig(&dcdc_config);
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dcdc_config.controlMode = kDCDC_SetPointControl;
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DCDC_Init(DCDC, &dcdc_config);
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}
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static void system_enter_sleep(gpc_cpu_mode_t gpc_mode)
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{
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__ASSERT_NO_MSG(gpc_mode != kGPC_RunMode);
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if (gpc_mode == kGPC_WaitMode) {
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/* Clear SLEEPDEEP bit to enter WAIT mode*/
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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} else {
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/* Set SLEEPDEEP bit to enter STOP mode */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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}
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/* When this function is entered the Kernel has disabled
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* interrupts using BASEPRI register. We will clear BASEPRI, and use PRIMASK
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* to disable interrupts, so that the WFI instruction works correctly.
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*/
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/* Set PRIMASK */
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__disable_irq();
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/* Set BASEPRI to 0 */
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irq_unlock(0);
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/* WFI instruction will start entry into WAIT/STOP mode */
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LOG_DBG("Entering LPM via WFI");
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__WFI();
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}
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void cpu_mode_transition(gpc_cpu_mode_t mode, bool enable_standby)
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{
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GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL, mode);
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GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL, true);
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/* Mask debugger wakeup */
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GPC_CPU_MODE_CTRL->CM_NON_IRQ_WAKEUP_MASK |=
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GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK |
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GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK;
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if (enable_standby) {
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/* Set standby request */
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GPC_CM_RequestStandbyMode(GPC_CPU_MODE_CTRL, mode);
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} else {
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/* Clear standby request */
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GPC_CM_ClearStandbyModeRequest(GPC_CPU_MODE_CTRL, mode);
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}
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/* Execute WFI- GPC will receive sleep request from CPU */
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system_enter_sleep(mode);
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}
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/**
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* SOC specific low power mode implementation
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* Drop to lowest power state possible given system's request
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*/
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(state);
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/* Extract set point and GPC mode from the substate ID */
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uint8_t set_point = IMX_SPC(substate_id);
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gpc_cpu_mode_t gpc_mode = IMX_GPC_MODE(substate_id);
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uint8_t current_set_point = GPC_SP_GetCurrentSetPoint(GPC_SET_POINT_CTRL);
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LOG_DBG("Switch to Set Point %d, GPC Mode %d requested", set_point, gpc_mode);
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if (gpc_mode != kGPC_RunMode && (current_set_point != set_point)) {
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/* Request set point transition at sleep */
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GPC_CM_RequestSleepModeSetPointTransition(GPC_CPU_MODE_CTRL,
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set_point, set_point, kGPC_CM_RequestPreviousSetpoint);
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cpu_mode_transition(gpc_mode, true);
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} else if (gpc_mode != kGPC_RunMode) {
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/* Request CPU mode transition without set mode transition */
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GPC_CM_RequestRunModeSetPointTransition(GPC_CPU_MODE_CTRL,
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current_set_point);
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cpu_mode_transition(gpc_mode, true);
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}
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}
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(state);
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ARG_UNUSED(substate_id);
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/* Clear PRIMASK */
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__enable_irq();
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LOG_DBG("Exiting LPM");
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LOG_DBG("CM7 mode was %d", GPC_CM_GetPreviousCpuMode(GPC_CPU_MODE_CTRL_0));
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LOG_DBG("CM4 mode was %d", GPC_CM_GetPreviousCpuMode(GPC_CPU_MODE_CTRL_1));
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LOG_DBG("Previous set point was %d", GPC_SP_GetPreviousSetPoint(GPC_SET_POINT_CTRL));
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}
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/* Initialize RT11xx Power */
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static int rt11xx_power_init(void)
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{
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/* Drop SOC target voltage to 1.0 V */
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DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P0V);
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/* Initialize general power controller */
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gpc_init();
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/* Initialize dcdc */
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dcdc_init();
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return 0;
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}
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SYS_INIT(rt11xx_power_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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