66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* Copyright (c) 2023, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <fsl_clock.h>
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#include <fsl_flexspi.h>
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#include <soc.h>
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#include <errno.h>
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#include <zephyr/irq.h>
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#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
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uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate)
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{
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clock_name_t root;
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uint32_t root_rate;
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FLEXSPI_Type *flexspi;
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clock_root_t flexspi_clk;
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clock_ip_name_t clk_gate;
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uint32_t divider;
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switch (clock_name) {
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case IMX_CCM_FLEXSPI_CLK:
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flexspi_clk = kCLOCK_Root_Flexspi1;
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flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi));
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clk_gate = kCLOCK_Flexspi1;
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break;
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case IMX_CCM_FLEXSPI2_CLK:
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flexspi_clk = kCLOCK_Root_Flexspi2;
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flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi2));
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clk_gate = kCLOCK_Flexspi2;
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break;
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default:
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return -ENOTSUP;
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}
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root = CLOCK_GetRootClockSource(flexspi_clk,
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CLOCK_GetRootClockMux(flexspi_clk));
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/* Get clock root frequency */
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root_rate = CLOCK_GetFreq(root);
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/* Select a divider based on root clock frequency. We round the
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* divider up, so that the resulting clock frequency is lower than
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* requested when we can't output the exact requested frequency
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*/
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divider = ((root_rate + (rate - 1)) / rate);
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/* Cap divider to max value */
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divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK);
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while (FLEXSPI_GetBusIdleStatus(flexspi) == false) {
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/* Spin */
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}
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FLEXSPI_Enable(flexspi, false);
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CLOCK_DisableClock(clk_gate);
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CLOCK_SetRootClockDiv(flexspi_clk, divider);
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CLOCK_EnableClock(clk_gate);
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FLEXSPI_Enable(flexspi, true);
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FLEXSPI_SoftwareReset(flexspi);
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return 0;
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}
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