110 lines
2.7 KiB
C
110 lines
2.7 KiB
C
/*
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* Copyright (c) 2021 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT andestech_l2c
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/**
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* @brief Andes V5 L2 Cache Controller driver
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*/
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#include "soc_v5.h"
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/syscon.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/arch/riscv/csr.h>
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LOG_MODULE_REGISTER(andes_v5_l2_cache, CONFIG_SOC_LOG_LEVEL);
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/* L2C Register Base Address */
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#define ANDES_V5_L2C_BASE DT_INST_REG_ADDR(0)
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/* L2C Register Offset */
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#define L2C_CONFIG (ANDES_V5_L2C_BASE + 0x00)
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#define L2C_CTRL (ANDES_V5_L2C_BASE + 0x08)
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/* L2C Helper Constant */
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#define L2C_CONFIG_VER GENMASK64(31, 24)
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#define L2C_CTRL_CEN BIT(0)
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/* Instruction prefetch depth */
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#define IPFDPT_FIELD(x) (x << 3)
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#define L2C_CTRL_IPFDPT_0 IPFDPT_FIELD(0)
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#define L2C_CTRL_IPFDPT_1 IPFDPT_FIELD(1)
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#define L2C_CTRL_IPFDPT_2 IPFDPT_FIELD(2)
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#define L2C_CTRL_IPFDPT_3 IPFDPT_FIELD(3)
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/* Data prefetch depth */
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#define DPFDPT_FIELD(x) (x << 5)
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#define L2C_CTRL_DPFDPT_0 DPFDPT_FIELD(0)
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#define L2C_CTRL_DPFDPT_2 DPFDPT_FIELD(1)
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#define L2C_CTRL_DPFDPT_4 DPFDPT_FIELD(2)
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#define L2C_CTRL_DPFDPT_8 DPFDPT_FIELD(3)
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#if DT_HAS_COMPAT_STATUS_OKAY(andestech_atcsmu100)
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/* SMU Register offset */
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#define SMU_SYSTEMCFG 0x08
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/* SMU Helper Constant */
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#define SMU_SYSTEMCFG_L2C BIT(8)
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#endif
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static void andes_v5_l2c_enable(void)
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{
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uint32_t l2c_ctrl = sys_read32(L2C_CTRL);
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/* Enable L2C if I-cache or D-cache is enabled */
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if (csr_read(NDS_MCACHE_CTL) & BIT_MASK(2)) {
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uint32_t l2c_config = sys_read32(L2C_CONFIG);
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/* Memory barrier, flush all I/D-Cache before setting L2C */
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__asm__ volatile ("fence.i");
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l2c_ctrl |= (L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8);
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sys_write32(l2c_ctrl, L2C_CTRL);
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/* Enable L2C for Gen1 L2C, Gen2 L2C defaults to enable */
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if ((l2c_config & L2C_CONFIG_VER) < (16 << 24)) {
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l2c_ctrl = sys_read32(L2C_CTRL);
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l2c_ctrl |= L2C_CTRL_CEN;
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sys_write32(l2c_ctrl, L2C_CTRL);
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}
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} else {
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/* Disable L2C */
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l2c_ctrl &= ~L2C_CTRL_CEN;
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sys_write32(l2c_ctrl, L2C_CTRL);
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}
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}
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static int andes_v5_l2c_init(void)
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{
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(syscon), andestech_atcsmu100, okay)
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const struct device *const syscon_dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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if (device_is_ready(syscon_dev)) {
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uint32_t system_cfg;
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syscon_read_reg(syscon_dev, SMU_SYSTEMCFG, &system_cfg);
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/* Platform doesn't have L2C */
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if (!(system_cfg & SMU_SYSTEMCFG_L2C)) {
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return -ENODEV;
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}
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} else {
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LOG_ERR("Syscon driver should be initialized before L2 Cache "
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"initialization.");
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}
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#endif
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andes_v5_l2c_enable();
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return 0;
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}
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SYS_INIT(andes_v5_l2c_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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