123 lines
2.9 KiB
Plaintext
123 lines
2.9 KiB
Plaintext
# Copyright (c) 2021 Andes Technology Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_ANDES_AE350
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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config SOC_ANDES_AE350
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select ATOMIC_OPERATIONS_BUILTIN
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select INCLUDE_RESET_VECTOR
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE
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select RISCV_PMP
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if SOC_SERIES_ANDES_AE350
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choice
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prompt "Base CPU ISA options"
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default RV32I_CPU
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config RV32I_CPU
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bool "RISCV32 CPU ISA"
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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config RV32E_CPU
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bool "RISCV32E CPU ISA"
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select RISCV_ISA_RV32E
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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config RV64I_CPU
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bool "RISCV64 CPU ISA"
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select RISCV_ISA_RV64I
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select 64BIT
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endchoice
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choice
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prompt "FPU options"
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default NO_FPU
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config NO_FPU
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bool "No FPU"
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config SINGLE_PRECISION_FPU
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bool "Single precision FPU"
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select CPU_HAS_FPU
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config DOUBLE_PRECISION_FPU
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bool "Double precision FPU"
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select CPU_HAS_FPU_DOUBLE_PRECISION
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endchoice
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config SOC_ANDES_V5_HWDSP
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bool "AndeStar V5 DSP ISA"
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select RISCV_SOC_CONTEXT_SAVE
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depends on !RISCV_GENERIC_TOOLCHAIN
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help
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This option enables the AndeStar v5 hardware DSP, in order to
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support using the DSP instructions.
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config SOC_ANDES_V5_PFT
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bool "Andes V5 PowerBrake extension"
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default y
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select RISCV_SOC_CONTEXT_SAVE
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help
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The PowerBrake extension throttles performance by reducing instruction
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executing rate.
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config SOC_ANDES_V5_EXECIT
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bool "Andes V5 EXEC.IT extension"
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depends on RISCV_ISA_EXT_C
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depends on !RISCV_GENERIC_TOOLCHAIN
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depends on !LINKER_USE_NO_RELAX
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help
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The EXEC.IT extension (Execution on Instruction Table) generate
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a look-up table and replaces suitable 32-bit instructions with
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the 16-bit "exec.it <INDEX>".
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config SOC_ANDES_V5_PMA
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bool "Andes V5 Physical Memory Attribute (PMA)"
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select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
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help
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This option enables the Andes V5 PMA, in order to support SW to
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configure physical memory attribute by PMA CSRs. The address
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matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
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(power-of-two alignment).
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config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE
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int
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depends on SOC_ANDES_V5_PMA
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default 4096
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help
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Minimum size (and alignment) of an PMA region. Use this symbol
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to guarantee minimum size and alignment of PMA regions.
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# Workaround for not being able to have commas in macro arguments
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DT_ANDESTECH_L2C := andestech,l2c
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config SOC_ANDES_V5_L2C
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bool
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default $(dt_compat_enabled,$(DT_ANDESTECH_L2C))
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config SOC_ANDES_V5_IOCP
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bool "Andes V5 I/O Coherence Port (IOCP)"
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depends on SOC_ANDES_V5_L2C
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depends on DCACHE
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help
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Support Andes V5 I/O Coherence Port to handle cache coherency
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between cache and external non-caching master, such as DMA
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controller.
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endif # SOC_SERIES_ANDES_AE350
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