298 lines
7.7 KiB
Plaintext
298 lines
7.7 KiB
Plaintext
# Kconfig - x86 general configuration options
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#
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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choice
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prompt "x86 SoC Selection"
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depends on X86
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source "arch/x86/soc/*/Kconfig.soc"
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endchoice
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menu "x86 Options"
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depends on X86
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config ARCH
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default "x86"
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config ARCH_DEFCONFIG
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string
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default "arch/x86/defconfig"
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source "arch/x86/core/Kconfig"
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#
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# Hidden CPU family configs which are to be selected by
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# individual SoC.
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#
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config CPU_ATOM
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# Hidden
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bool
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select CMOV
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select CPU_HAS_FPU
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help
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This option signifies the use of a CPU from the Atom family.
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config CPU_MINUTEIA
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# Hidden
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bool
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help
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This option signifies the use of a CPU from the Minute IA family.
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#
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# End hidden CPU family configs
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#
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config CPU_HAS_FPU
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# Hidden config selected by CPU family
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bool
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default n
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help
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This option is enabled when the CPU has hardware floating point
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unit.
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menu "Processor Capabilities"
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config X86_IAMCU
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bool
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default n
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prompt "IAMCU calling convention"
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help
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The IAMCU calling convention changes the X86 C calling convention to
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pass some arguments via registers allowing for code size and performance
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improvements. Great care needs to be taken if you have assembly code
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that will be called from C or C code called from assembly code, the
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assembly code will need to be updated to conform to the new calling
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convention. If in doubt say N
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menu "Floating Point Options"
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depends on CPU_HAS_FPU
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config FLOAT
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bool
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prompt "Floating point registers"
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default n
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help
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This option allows tasks and fibers to use the floating point registers.
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By default, only a single task or fiber may use the registers, and only
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the x87 FPU/MMX registers may be used.
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Disabling this option means that any task or fiber that uses a
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floating point register will get a fatal exception.
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config FP_SHARING
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bool
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prompt "Floating point register sharing"
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depends on FLOAT
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default n
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help
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This option allows multiple tasks and fibers to use the floating point
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registers. Any task that uses the floating point registers must provide
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stack space where the kernel can save these registers during context
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switches; a task that uses only the x87 FPU/MMX registers must provide
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108 bytes of added stack space, while a task the uses the SSE registers
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must provide 464 bytes of added stack space.
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config SSE
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bool
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prompt "SSE registers"
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depends on FLOAT
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default n
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help
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This option enables the use of SSE registers by tasks and fibers.
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config SSE_FP_MATH
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bool
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prompt "Compiler-generated SSEx instructions"
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depends on SSE
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default n
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help
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This option allows the compiler to generate SSEx instructions for
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performing floating point math. This can greatly improve performance
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when exactly the same operations are to be performed on multiple
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data objects; however, it can also significantly reduce performance
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when pre-emptive task switches occur because of the larger register
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set that must be saved and restored.
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Disabling this option means that the compiler utilizes only the
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x87 instruction set for floating point operations.
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endmenu
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choice
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prompt "Reboot implementation"
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depends on REBOOT
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default REBOOT_RST_CNT
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config REBOOT_RST_CNT
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bool
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prompt "Reboot via RST_CNT register"
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help
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Reboot via the RST_CNT register, going back to BIOS.
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endchoice
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config ISA_IA32
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bool
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default y
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help
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This option signifies the use of a CPU based on the Intel IA-32
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instruction set architecture.
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config IA32_LEGACY_IO_PORTS
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bool
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prompt "Support IA32 legacy IO ports"
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default n
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depends on ISA_IA32
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help
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This option enables IA32 legacy IO ports. Note these are much slower
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than memory access, so they should be used in last resort.
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config CMOV
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def_bool n
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help
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This option signifies the use of an Intel CPU that supports
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the CMOV instruction.
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config CACHE_LINE_SIZE_DETECT
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bool
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prompt "Detect cache line size at runtime"
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default y
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help
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This option enables querying the CPUID register for finding the cache line
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size at the expense of taking more memory and code and a slightly increased
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boot time.
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If the CPU's cache line size is known in advance, disable this option and
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manually enter the value for CACHE_LINE_SIZE.
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config CACHE_LINE_SIZE
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int
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prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
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default 0 if CACHE_LINE_SIZE_DETECT
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default 64 if CPU_ATOM
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default 0
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help
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Size in bytes of a CPU cache line.
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Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
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config CLFLUSH_INSTRUCTION_SUPPORTED
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bool
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prompt "CLFLUSH instruction supported"
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depends on !CLFLUSH_DETECT && CACHE_FLUSHING
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default n
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help
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An implementation of sys_cache_flush() that uses CLFLUSH is made
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available, instead of the one using WBINVD.
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This option should only be enabled if it is known in advance that the
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CPU supports the CLFLUSH instruction. It disables runtime detection of
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CLFLUSH support thereby reducing both memory footprint and boot time.
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config CLFLUSH_DETECT
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bool
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prompt "Detect support of CLFLUSH instruction at runtime"
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depends on CACHE_FLUSHING
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default n
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help
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This option should be enabled if it is not known in advance whether the
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CPU supports the CLFLUSH instruction or not.
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The CPU is queried at boot time to determine which of the multiple
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implementations of sys_cache_flush() linked into the image is the
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correct one to use.
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If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
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disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
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config ARCH_CACHE_FLUSH_DETECT
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bool
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default y
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depends on CLFLUSH_DETECT
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config CACHE_FLUSHING
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bool
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default n
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prompt "Enable cache flushing mechanism"
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help
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This links in the sys_cache_flush() function. A mechanism for flushing the
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cache must be selected as well. By default, that mechanism is discovered at
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runtime.
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endmenu
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menu "Platform Capabilities"
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config NUM_DYNAMIC_STUBS
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int "Number of dynamic int stubs"
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default 0
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help
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This option specifies the number of interrupt handlers that can be
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installed dynamically using irq_connect_dynamic().
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config NUM_DYNAMIC_EXC_STUBS
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int "Number of dynamic exception stubs"
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default 0
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help
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This option specifies the maximum number of dynamically allocated
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exception stubs that are to be used with exceptions that push an
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error code onto the stack.
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config NUM_DYNAMIC_EXC_NOERR_STUBS
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int "Number of dynamic no-error exception stubs"
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default 0
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help
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This option specifies the maximum number of dynamically allocated
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exception stubs that are to be used with exceptions that do not push
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an error code onto the stack.
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config PIC_DISABLE
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bool "Disable PIC"
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default n
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help
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This option disables all interrupts on the PIC
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config IRQ_OFFLOAD
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bool "Enable IRQ offload"
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default n
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help
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Enable irq_offload() API which allows functions to be synchronously
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run in interrupt context. Uses one entry in the IDT. Mainly useful
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for test cases.
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config IRQ_OFFLOAD_VECTOR
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int "IDT vector to use for IRQ offload"
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default 63 if MVIC
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default 32 if !MVIC
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range 32 255
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depends on IRQ_OFFLOAD
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help
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Specify the IDT vector to use for the IRQ offload interrupt handler.
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The default should be fine for most arches, but on systems like MVIC
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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config XIP
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default n
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endmenu
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source "arch/x86/soc/*/Kconfig"
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endmenu
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