355 lines
11 KiB
C
355 lines
11 KiB
C
/*
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* system.h - SOPC Builder system and BSP software package information
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*
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* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
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* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
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*
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* Generated: Wed Jun 08 19:18:29 MYT 2016
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*/
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/*
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* DO NOT MODIFY THIS FILE
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*
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* Changing this file will have subtle consequences
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* which will almost certainly lead to a nonfunctioning
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* system. If you do modify this file, be aware that your
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* changes will be overwritten and lost when this file
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* is generated again.
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*
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* DO NOT MODIFY THIS FILE
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*/
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/*
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* License Agreement
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*
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* Copyright (c) 2008
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* Altera Corporation, San Jose, California, USA.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* This agreement shall be governed in all respects by the laws of the State
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* of California and by the laws of the United States of America.
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*/
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#ifndef __SYSTEM_H_
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#define __SYSTEM_H_
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/* Include definitions from linker script generator */
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#include "linker.h"
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/*
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* CPU configuration
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*
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*/
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#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
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#define ALT_CPU_BIG_ENDIAN 0
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#define ALT_CPU_BREAK_ADDR 0x00200820
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#define ALT_CPU_CPU_ARCH_NIOS2_R1
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#define ALT_CPU_CPU_FREQ 50000000u
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#define ALT_CPU_CPU_ID_SIZE 1
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#define ALT_CPU_CPU_ID_VALUE 0x00000000
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#define ALT_CPU_CPU_IMPLEMENTATION "fast"
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#define ALT_CPU_DATA_ADDR_WIDTH 0x17
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#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
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#define ALT_CPU_DCACHE_LINE_SIZE 32
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#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
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#define ALT_CPU_DCACHE_SIZE 2048
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#define ALT_CPU_EXCEPTION_ADDR 0x00400020
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#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
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#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
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#define ALT_CPU_FLUSHDA_SUPPORTED
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#define ALT_CPU_FREQ 50000000
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#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 1
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#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
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#define ALT_CPU_HARDWARE_MULX_PRESENT 0
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#define ALT_CPU_HAS_DEBUG_CORE 1
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#define ALT_CPU_HAS_DEBUG_STUB
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#define ALT_CPU_HAS_DIVISION_ERROR_EXCEPTION
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#define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO
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#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
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#define ALT_CPU_HAS_JMPI_INSTRUCTION
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#define ALT_CPU_ICACHE_LINE_SIZE 32
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#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
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#define ALT_CPU_ICACHE_SIZE 4096
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#define ALT_CPU_INITDA_SUPPORTED
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#define ALT_CPU_INST_ADDR_WIDTH 0x17
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#define ALT_CPU_NAME "nios2_gen2_0"
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#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
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#define ALT_CPU_OCI_VERSION 1
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#define ALT_CPU_RESET_ADDR 0x00000000
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/*
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* CPU configuration (with legacy prefix - don't use these anymore)
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*
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*/
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#define NIOS2_BIG_ENDIAN 0
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#define NIOS2_BREAK_ADDR 0x00200820
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#define NIOS2_CPU_ARCH_NIOS2_R1
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#define NIOS2_CPU_FREQ 50000000u
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#define NIOS2_CPU_ID_SIZE 1
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#define NIOS2_CPU_ID_VALUE 0x00000000
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#define NIOS2_CPU_IMPLEMENTATION "fast"
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#define NIOS2_DATA_ADDR_WIDTH 0x17
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#define NIOS2_DCACHE_BYPASS_MASK 0x80000000
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#define NIOS2_DCACHE_LINE_SIZE 32
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#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
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#define NIOS2_DCACHE_SIZE 2048
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#define NIOS2_EXCEPTION_ADDR 0x00400020
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#define NIOS2_FLASH_ACCELERATOR_LINES 0
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#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
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#define NIOS2_FLUSHDA_SUPPORTED
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#define NIOS2_HARDWARE_DIVIDE_PRESENT 1
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#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
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#define NIOS2_HARDWARE_MULX_PRESENT 0
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#define NIOS2_HAS_DEBUG_CORE 1
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#define NIOS2_HAS_DEBUG_STUB
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#define NIOS2_HAS_DIVISION_ERROR_EXCEPTION
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#define NIOS2_HAS_EXTRA_EXCEPTION_INFO
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#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
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#define NIOS2_HAS_JMPI_INSTRUCTION
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#define NIOS2_ICACHE_LINE_SIZE 32
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#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
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#define NIOS2_ICACHE_SIZE 4096
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#define NIOS2_INITDA_SUPPORTED
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#define NIOS2_INST_ADDR_WIDTH 0x17
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#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
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#define NIOS2_OCI_VERSION 1
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#define NIOS2_RESET_ADDR 0x00000000
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/*
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* Define for each module class mastered by the CPU
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*
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*/
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#define __ALTERA_16550_UART
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#define __ALTERA_AVALON_JTAG_UART
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#define __ALTERA_AVALON_ONCHIP_MEMORY2
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#define __ALTERA_AVALON_TIMER
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#define __ALTERA_NIOS2_GEN2
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#define __ALTERA_ONCHIP_FLASH
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/*
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* System configuration
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*
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*/
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#define ALT_DEVICE_FAMILY "MAX 10"
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#define ALT_ENHANCED_INTERRUPT_API_PRESENT
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#define ALT_IRQ_BASE NULL
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#define ALT_LOG_PORT "/dev/null"
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#define ALT_LOG_PORT_BASE 0x0
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#define ALT_LOG_PORT_DEV null
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#define ALT_LOG_PORT_TYPE ""
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#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
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#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
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#define ALT_NUM_INTERRUPT_CONTROLLERS 1
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#define ALT_STDERR "/dev/jtag_uart_0"
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#define ALT_STDERR_BASE 0x201000
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#define ALT_STDERR_DEV jtag_uart_0
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#define ALT_STDERR_IS_JTAG_UART
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#define ALT_STDERR_PRESENT
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#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
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#define ALT_STDIN "/dev/jtag_uart_0"
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#define ALT_STDIN_BASE 0x201000
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#define ALT_STDIN_DEV jtag_uart_0
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#define ALT_STDIN_IS_JTAG_UART
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#define ALT_STDIN_PRESENT
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#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
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#define ALT_STDOUT "/dev/jtag_uart_0"
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#define ALT_STDOUT_BASE 0x201000
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#define ALT_STDOUT_DEV jtag_uart_0
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#define ALT_STDOUT_IS_JTAG_UART
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#define ALT_STDOUT_PRESENT
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#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
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#define ALT_SYSTEM_NAME "ghrd_10m50da"
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/*
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* a_16550_uart_0 configuration
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*
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*/
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#define ALT_MODULE_CLASS_a_16550_uart_0 altera_16550_uart
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#define A_16550_UART_0_BASE 0x440000
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#define A_16550_UART_0_FIFO_DEPTH 64
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#define A_16550_UART_0_FIFO_MODE 1
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#define A_16550_UART_0_FIO_HWFC 0
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#define A_16550_UART_0_FIO_SWFC 0
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#define A_16550_UART_0_FREQ 50000000
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#define A_16550_UART_0_IRQ 1
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#define A_16550_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define A_16550_UART_0_NAME "/dev/a_16550_uart_0"
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#define A_16550_UART_0_SPAN 512
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#define A_16550_UART_0_TYPE "altera_16550_uart"
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/*
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* hal configuration
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*
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*/
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#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
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#define ALT_MAX_FD 32
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#define ALT_SYS_CLK TIMER_0
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#define ALT_TIMESTAMP_CLK none
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/*
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* jtag_uart_0 configuration
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*
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*/
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#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
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#define JTAG_UART_0_BASE 0x201000
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#define JTAG_UART_0_IRQ 0
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#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
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#define JTAG_UART_0_READ_DEPTH 64
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#define JTAG_UART_0_READ_THRESHOLD 8
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#define JTAG_UART_0_SPAN 8
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#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
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#define JTAG_UART_0_WRITE_DEPTH 64
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#define JTAG_UART_0_WRITE_THRESHOLD 8
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/*
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* onchip_flash_0_csr configuration
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*
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*/
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#define ALT_MODULE_CLASS_onchip_flash_0_csr altera_onchip_flash
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#define ONCHIP_FLASH_0_CSR_BASE 0x200000
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#define ONCHIP_FLASH_0_CSR_BYTES_PER_PAGE 8192
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#define ONCHIP_FLASH_0_CSR_IRQ -1
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#define ONCHIP_FLASH_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define ONCHIP_FLASH_0_CSR_NAME "/dev/onchip_flash_0_csr"
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#define ONCHIP_FLASH_0_CSR_READ_ONLY_MODE 0
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#define ONCHIP_FLASH_0_CSR_SECTOR1_ENABLED 1
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#define ONCHIP_FLASH_0_CSR_SECTOR1_END_ADDR 0x7fff
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#define ONCHIP_FLASH_0_CSR_SECTOR1_START_ADDR 0
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#define ONCHIP_FLASH_0_CSR_SECTOR2_ENABLED 1
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#define ONCHIP_FLASH_0_CSR_SECTOR2_END_ADDR 0xffff
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#define ONCHIP_FLASH_0_CSR_SECTOR2_START_ADDR 0x8000
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#define ONCHIP_FLASH_0_CSR_SECTOR3_ENABLED 1
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#define ONCHIP_FLASH_0_CSR_SECTOR3_END_ADDR 0x6ffff
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#define ONCHIP_FLASH_0_CSR_SECTOR3_START_ADDR 0x10000
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#define ONCHIP_FLASH_0_CSR_SECTOR4_ENABLED 1
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#define ONCHIP_FLASH_0_CSR_SECTOR4_END_ADDR 0xb7fff
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#define ONCHIP_FLASH_0_CSR_SECTOR4_START_ADDR 0x70000
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#define ONCHIP_FLASH_0_CSR_SECTOR5_ENABLED 0
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#define ONCHIP_FLASH_0_CSR_SECTOR5_END_ADDR 0xffffffff
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#define ONCHIP_FLASH_0_CSR_SECTOR5_START_ADDR 0xffffffff
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#define ONCHIP_FLASH_0_CSR_SPAN 8
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#define ONCHIP_FLASH_0_CSR_TYPE "altera_onchip_flash"
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/*
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* onchip_flash_0_data configuration
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*
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*/
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#define ALT_MODULE_CLASS_onchip_flash_0_data altera_onchip_flash
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#define ONCHIP_FLASH_0_DATA_BASE 0x0
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#define ONCHIP_FLASH_0_DATA_BYTES_PER_PAGE 8192
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#define ONCHIP_FLASH_0_DATA_IRQ -1
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#define ONCHIP_FLASH_0_DATA_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define ONCHIP_FLASH_0_DATA_NAME "/dev/onchip_flash_0_data"
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#define ONCHIP_FLASH_0_DATA_READ_ONLY_MODE 0
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#define ONCHIP_FLASH_0_DATA_SECTOR1_ENABLED 1
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#define ONCHIP_FLASH_0_DATA_SECTOR1_END_ADDR 0x7fff
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#define ONCHIP_FLASH_0_DATA_SECTOR1_START_ADDR 0
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#define ONCHIP_FLASH_0_DATA_SECTOR2_ENABLED 1
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#define ONCHIP_FLASH_0_DATA_SECTOR2_END_ADDR 0xffff
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#define ONCHIP_FLASH_0_DATA_SECTOR2_START_ADDR 0x8000
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#define ONCHIP_FLASH_0_DATA_SECTOR3_ENABLED 1
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#define ONCHIP_FLASH_0_DATA_SECTOR3_END_ADDR 0x6ffff
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#define ONCHIP_FLASH_0_DATA_SECTOR3_START_ADDR 0x10000
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#define ONCHIP_FLASH_0_DATA_SECTOR4_ENABLED 1
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#define ONCHIP_FLASH_0_DATA_SECTOR4_END_ADDR 0xb7fff
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#define ONCHIP_FLASH_0_DATA_SECTOR4_START_ADDR 0x70000
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#define ONCHIP_FLASH_0_DATA_SECTOR5_ENABLED 0
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#define ONCHIP_FLASH_0_DATA_SECTOR5_END_ADDR 0xffffffff
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#define ONCHIP_FLASH_0_DATA_SECTOR5_START_ADDR 0xffffffff
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#define ONCHIP_FLASH_0_DATA_SPAN 753664
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#define ONCHIP_FLASH_0_DATA_TYPE "altera_onchip_flash"
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/*
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* onchip_memory2_0 configuration
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*
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*/
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#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2
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#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
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#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
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#define ONCHIP_MEMORY2_0_BASE 0x400000
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#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
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#define ONCHIP_MEMORY2_0_DUAL_PORT 0
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#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO"
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#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "ghrd_10m50da_onchip_memory2_0"
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#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 0
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#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"
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#define ONCHIP_MEMORY2_0_IRQ -1
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#define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0"
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#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
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#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "AUTO"
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#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
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#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
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#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
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#define ONCHIP_MEMORY2_0_SIZE_VALUE 167936
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#define ONCHIP_MEMORY2_0_SPAN 167936
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#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
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#define ONCHIP_MEMORY2_0_WRITABLE 1
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/*
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* timer_0 configuration
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*
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*/
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#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
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#define TIMER_0_ALWAYS_RUN 0
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#define TIMER_0_BASE 0x440200
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#define TIMER_0_COUNTER_SIZE 32
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#define TIMER_0_FIXED_PERIOD 0
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#define TIMER_0_FREQ 50000000
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#define TIMER_0_IRQ 2
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#define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define TIMER_0_LOAD_VALUE 49999
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#define TIMER_0_MULT 0.001
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#define TIMER_0_NAME "/dev/timer_0"
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#define TIMER_0_PERIOD 1
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#define TIMER_0_PERIOD_UNITS "ms"
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#define TIMER_0_RESET_OUTPUT 0
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#define TIMER_0_SNAPSHOT 1
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#define TIMER_0_SPAN 32
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#define TIMER_0_TICKS_PER_SEC 1000
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#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
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#define TIMER_0_TYPE "altera_avalon_timer"
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#endif /* __SYSTEM_H_ */
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