415 lines
10 KiB
C
415 lines
10 KiB
C
/*
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* Copyright (c) 2019, Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT aptina_mt9m114
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#include <zephyr/zephyr.h>
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#include <zephyr/device.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/drivers/video.h>
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#include <zephyr/drivers/i2c.h>
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#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(mt9m114);
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#define MT9M114_CHIP_ID_VAL 0x2481
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/* Sysctl registers */
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#define MT9M114_CHIP_ID 0x0000
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#define MT9M114_COMMAND_REGISTER 0x0080
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#define MT9M114_COMMAND_REGISTER_APPLY_PATCH (1 << 0)
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#define MT9M114_COMMAND_REGISTER_SET_STATE (1 << 1)
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#define MT9M114_COMMAND_REGISTER_REFRESH (1 << 2)
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#define MT9M114_COMMAND_REGISTER_WAIT_FOR_EVENT (1 << 3)
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#define MT9M114_COMMAND_REGISTER_OK (1 << 15)
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#define MT9M114_PAD_CONTROL 0x0032
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#define MT9M114_RST_AND_MISC_CONTROL 0x001A
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/* Camera Control registers */
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#define MT9M114_CAM_OUTPUT_FORMAT 0xc86c
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/* System Manager registers */
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#define MT9M114_SYSMGR_NEXT_STATE 0xdc00
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#define MT9M114_SYSMGR_CURRENT_STATE 0xdc01
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#define MT9M114_SYSMGR_CMD_STATUS 0xdc02
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/* System States */
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#define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28
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#define MT9M114_SYS_STATE_STREAMING 0x31
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#define MT9M114_SYS_STATE_START_STREAMING 0x34
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#define MT9M114_SYS_STATE_ENTER_SUSPEND 0x40
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#define MT9M114_SYS_STATE_SUSPENDED 0x41
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#define MT9M114_SYS_STATE_ENTER_STANDBY 0x50
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#define MT9M114_SYS_STATE_STANDBY 0x52
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#define MT9M114_SYS_STATE_LEAVE_STANDBY 0x54
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struct mt9m114_config {
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struct i2c_dt_spec i2c;
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};
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struct mt9m114_data {
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struct video_format fmt;
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};
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struct mt9m114_reg {
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uint16_t addr;
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uint16_t value_size;
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uint32_t value;
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};
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static struct mt9m114_reg mt9m114_vga_24mhz_pll[] = {
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{ 0x98E, 2, 0x1000 },
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{ 0xC97E, 2, 0x01 }, /* cam_sysctl_pll_enable = 1 */
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{ 0xC980, 2, 0x0120 }, /* cam_sysctl_pll_divider_m_n = 288 */
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{ 0xC982, 2, 0x0700 }, /* cam_sysctl_pll_divider_p = 1792 */
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{ 0xC984, 2, 0x8000 }, /* cam_port_output_control = 32776 */
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{ 0xC800, 2, 0x0000 }, /* cam_sensor_cfg_y_addr_start = 0 */
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{ 0xC802, 2, 0x0000 }, /* cam_sensor_cfg_x_addr_start = 0 */
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{ 0xC804, 2, 0x03CD }, /* cam_sensor_cfg_y_addr_end = 973 */
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{ 0xC806, 2, 0x050D }, /* cam_sensor_cfg_x_addr_end = 1293 */
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{ 0xC808, 4, 0x2DC6C00 }, /* cam_sensor_cfg_pixclk = 48000000 */
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{ 0xC80C, 2, 0x0001 }, /* cam_sensor_cfg_row_speed = 1 */
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{ 0xC80E, 2, 0x00DB }, /* cam_sensor_cfg_fine_integ_min = 219 */
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{ 0xC810, 2, 0x07C2 }, /* cam_sensor_cfg_fine_integ_max = 1986 */
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{ 0xC812, 2, 0x02FE }, /* cam_sensor_cfg_frame_length_lines = 766 */
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{ 0xC814, 2, 0x0845 }, /* cam_sensor_cfg_line_length_pck = 2117 */
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{ 0xC816, 2, 0x0060 }, /* cam_sensor_cfg_fine_correction = 96 */
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{ 0xC818, 2, 0x01E3 }, /* cam_sensor_cfg_cpipe_last_row = 483 */
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{ 0xC826, 2, 0x0020 }, /* cam_sensor_cfg_reg_0_data = 32 */
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{ 0xC834, 2, 0x0110 }, /* cam_sensor_control_read_mode = 272 */
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{ 0xC854, 2, 0x0000 }, /* cam_crop_window_xoffset = 0 */
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{ 0xC856, 2, 0x0000 }, /* cam_crop_window_yoffset = 0 */
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{ 0xC858, 2, 0x0280 }, /* cam_crop_window_width = 640 */
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{ 0xC85A, 2, 0x01E0 }, /* cam_crop_window_height = 480 */
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{ 0xC85C, 1, 0x03 }, /* cam_crop_cropmode = 3 */
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{ 0xC868, 2, 0x0280 }, /* cam_output_width = 640 */
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{ 0xC86A, 2, 0x01E0 }, /* cam_output_height = 480 */
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{ 0xC878, 1, 0x00 }, /* cam_aet_aemode = 0 */
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{ 0xC88C, 2, 0x1D9A }, /* cam_aet_max_frame_rate = 7578 */
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{ 0xC914, 2, 0x0000 }, /* cam_stat_awb_clip_window_xstart = 0 */
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{ 0xC88E, 2, 0x1D9A }, /* cam_aet_min_frame_rate = 7578 */
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{ 0xC916, 2, 0x0000 }, /* cam_stat_awb_clip_window_ystart = 0 */
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{ 0xC918, 2, 0x027F }, /* cam_stat_awb_clip_window_xend = 639 */
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{ 0xC91A, 2, 0x01DF }, /* cam_stat_awb_clip_window_yend = 479 */
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{ 0xC91C, 2, 0x0000 }, /* cam_stat_ae_initial_window_xstart = 0 */
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{ 0xC91E, 2, 0x0000 }, /* cam_stat_ae_initial_window_ystart = 0 */
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{ 0xC920, 2, 0x007F }, /* cam_stat_ae_initial_window_xend = 127 */
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{ 0xC922, 2, 0x005F }, /* cam_stat_ae_initial_window_yend = 95 */
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{ /* NULL terminated */ }
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};
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static inline int i2c_burst_read16_dt(const struct i2c_dt_spec *spec,
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uint16_t start_addr, uint8_t *buf, uint32_t num_bytes)
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{
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uint8_t addr_buffer[2];
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addr_buffer[1] = start_addr & 0xFF;
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addr_buffer[0] = start_addr >> 8;
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return i2c_write_read_dt(spec, addr_buffer, sizeof(addr_buffer), buf, num_bytes);
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}
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static inline int i2c_burst_write16_dt(const struct i2c_dt_spec *spec,
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uint16_t start_addr, const uint8_t *buf,
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uint32_t num_bytes)
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{
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uint8_t addr_buffer[2];
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struct i2c_msg msg[2];
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addr_buffer[1] = start_addr & 0xFF;
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addr_buffer[0] = start_addr >> 8;
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msg[0].buf = addr_buffer;
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msg[0].len = 2U;
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msg[0].flags = I2C_MSG_WRITE;
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msg[1].buf = (uint8_t *)buf;
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msg[1].len = num_bytes;
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msg[1].flags = I2C_MSG_WRITE | I2C_MSG_STOP;
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return i2c_transfer_dt(spec, msg, 2);
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}
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static int mt9m114_write_reg(const struct device *dev, uint16_t reg_addr,
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uint8_t reg_size,
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void *value)
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{
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const struct mt9m114_config *cfg = dev->config;
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switch (reg_size) {
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case 2:
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*(uint16_t *)value = sys_cpu_to_be16(*(uint16_t *)value);
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break;
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case 4:
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*(uint16_t *)value = sys_cpu_to_be32(*(uint16_t *)value);
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break;
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case 1:
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break;
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default:
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return -ENOTSUP;
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}
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return i2c_burst_write16_dt(&cfg->i2c, reg_addr, value, reg_size);
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}
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static int mt9m114_read_reg(const struct device *dev, uint16_t reg_addr,
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uint8_t reg_size,
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void *value)
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{
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const struct mt9m114_config *cfg = dev->config;
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int err;
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if (reg_size > 4) {
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return -ENOTSUP;
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}
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err = i2c_burst_read16_dt(&cfg->i2c, reg_addr, value, reg_size);
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if (err) {
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return err;
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}
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switch (reg_size) {
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case 2:
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*(uint16_t *)value = sys_be16_to_cpu(*(uint16_t *)value);
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break;
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case 4:
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*(uint32_t *)value = sys_be32_to_cpu(*(uint32_t *)value);
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break;
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case 1:
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int mt9m114_write_all(const struct device *dev,
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struct mt9m114_reg *reg)
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{
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int i = 0;
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while (reg[i].value_size) {
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int err;
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err = mt9m114_write_reg(dev, reg[i].addr, reg[i].value_size,
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®[i].value);
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if (err) {
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return err;
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}
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i++;
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}
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return 0;
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}
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static int mt9m114_set_state(const struct device *dev, uint8_t state)
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{
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uint16_t val;
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int err;
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/* Set next state. */
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mt9m114_write_reg(dev, MT9M114_SYSMGR_NEXT_STATE, 1, &state);
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/* Check that the FW is ready to accept a new command. */
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while (1) {
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err = mt9m114_read_reg(dev, MT9M114_COMMAND_REGISTER, 2, &val);
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if (err) {
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return err;
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}
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if (!(val & MT9M114_COMMAND_REGISTER_SET_STATE)) {
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break;
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}
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k_sleep(K_MSEC(1));
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}
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/* Issue the Set State command. */
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val = MT9M114_COMMAND_REGISTER_SET_STATE | MT9M114_COMMAND_REGISTER_OK;
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mt9m114_write_reg(dev, MT9M114_COMMAND_REGISTER, 2, &val);
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/* Wait for the FW to complete the command. */
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while (1) {
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err = mt9m114_read_reg(dev, MT9M114_COMMAND_REGISTER, 2, &val);
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if (err) {
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return err;
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}
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if (!(val & MT9M114_COMMAND_REGISTER_SET_STATE)) {
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break;
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}
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k_sleep(K_MSEC(1));
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}
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/* Check the 'OK' bit to see if the command was successful. */
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err = mt9m114_read_reg(dev, MT9M114_COMMAND_REGISTER, 2, &val);
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if (err || !(val & MT9M114_COMMAND_REGISTER_OK)) {
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return -EIO;
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}
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return 0;
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}
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static int mt9m114_set_fmt(const struct device *dev,
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enum video_endpoint_id ep,
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struct video_format *fmt)
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{
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struct mt9m114_data *drv_data = dev->data;
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uint16_t output_format;
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int ret;
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/* we only support one format for now (VGA RGB565) */
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if (fmt->pixelformat != VIDEO_PIX_FMT_RGB565 || fmt->height != 480 ||
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fmt->width != 640) {
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return -ENOTSUP;
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}
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if (!memcmp(&drv_data->fmt, fmt, sizeof(drv_data->fmt))) {
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/* nothing to do */
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return 0;
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}
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drv_data->fmt = *fmt;
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/* Configure Sensor */
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ret = mt9m114_write_all(dev, mt9m114_vga_24mhz_pll);
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if (ret) {
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LOG_ERR("Unable to write mt9m114 config");
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return ret;
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}
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/* Set output format */
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output_format = ((1U << 8U) | (1U << 1U)); /* RGB565 */
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ret = mt9m114_write_reg(dev, MT9M114_CAM_OUTPUT_FORMAT,
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sizeof(output_format), &output_format);
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if (ret) {
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LOG_ERR("Unable to set output format");
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return ret;
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}
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/* Apply Config */
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mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE);
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return 0;
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}
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static int mt9m114_get_fmt(const struct device *dev,
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enum video_endpoint_id ep,
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struct video_format *fmt)
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{
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struct mt9m114_data *drv_data = dev->data;
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*fmt = drv_data->fmt;
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return 0;
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}
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static int mt9m114_stream_start(const struct device *dev)
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{
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return mt9m114_set_state(dev, MT9M114_SYS_STATE_START_STREAMING);
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}
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static int mt9m114_stream_stop(const struct device *dev)
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{
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return mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_SUSPEND);
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}
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static const struct video_format_cap fmts[] = {
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{
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.pixelformat = VIDEO_PIX_FMT_RGB565,
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.width_min = 640,
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.width_max = 640,
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.height_min = 480,
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.height_max = 480,
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.width_step = 0,
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.height_step = 0,
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},
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{ 0 }
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};
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static int mt9m114_get_caps(const struct device *dev,
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enum video_endpoint_id ep,
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struct video_caps *caps)
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{
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caps->format_caps = fmts;
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return 0;
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}
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static const struct video_driver_api mt9m114_driver_api = {
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.set_format = mt9m114_set_fmt,
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.get_format = mt9m114_get_fmt,
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.get_caps = mt9m114_get_caps,
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.stream_start = mt9m114_stream_start,
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.stream_stop = mt9m114_stream_stop,
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};
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static int mt9m114_init(const struct device *dev)
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{
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struct video_format fmt;
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uint16_t val;
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int ret;
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/* no power control, wait for camera ready */
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k_sleep(K_MSEC(100));
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ret = mt9m114_read_reg(dev, MT9M114_CHIP_ID, sizeof(val), &val);
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if (ret) {
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LOG_ERR("Unable to read chip ID");
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return -ENODEV;
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}
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if (val != MT9M114_CHIP_ID_VAL) {
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LOG_ERR("Wrong ID: %04x (exp %04x)", val, MT9M114_CHIP_ID_VAL);
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return -ENODEV;
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}
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/* set default/init format VGA RGB565 */
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fmt.pixelformat = VIDEO_PIX_FMT_RGB565;
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fmt.width = 640;
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fmt.height = 480;
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fmt.pitch = 640 * 2;
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ret = mt9m114_set_fmt(dev, VIDEO_EP_OUT, &fmt);
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if (ret) {
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LOG_ERR("Unable to configure default format");
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return -EIO;
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}
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/* Suspend any stream */
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mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_SUSPEND);
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return 0;
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}
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#if 1 /* Unique Instance */
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static const struct mt9m114_config mt9m114_cfg_0 = {
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.i2c = I2C_DT_SPEC_INST_GET(0),
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};
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static struct mt9m114_data mt9m114_data_0;
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static int mt9m114_init_0(const struct device *dev)
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{
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const struct mt9m114_config *cfg = dev->config;
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if (!device_is_ready(cfg->i2c.bus)) {
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LOG_ERR("Bus device is not ready");
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return -ENODEV;
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}
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return mt9m114_init(dev);
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}
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DEVICE_DT_INST_DEFINE(0, &mt9m114_init_0, NULL,
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&mt9m114_data_0, &mt9m114_cfg_0,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&mt9m114_driver_api);
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#endif
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