98 lines
2.7 KiB
ReStructuredText
98 lines
2.7 KiB
ReStructuredText
.. _qemu_cortex_m3:
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Board Configuration: qemu_cortex_m3
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#######################################
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Overview
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********
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The Zephyr kernel uses the qemu_cortex_m3 board configuration
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to emulate the TI LM3S6965 platform running on QEMU. It provides support
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for an ARM Cortex-M3 CPU and the following devices:
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* Nested Vectored Interrupt Controller
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* System Tick System Clock
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* Stellaris UART
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.. note::
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This board configuration makes no claims about its suitability for use
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with an actual ti_lm3s6965 hardware system, or any other hardware system.
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Supported Boards
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****************
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The qemu_cortex_m3 board configuration has been tested on
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QEMU 2.1 patched with Zephyr's
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:file:`0001-armv7m-support-basepri-primask-interrupt-locking.patch`.
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Supported Features
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******************
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The qemu_cortex_m3 board configuration supports the following
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hardware features:
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+--------------+------------+----------------------+
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| Interface | Controller | Driver/Component |
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+==============+============+======================+
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| NVIC | on-chip | nested vectored |
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| | | interrupt controller |
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+--------------+------------+----------------------+
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| Stellaris | on-chip | serial port |
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| UART | | |
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+--------------+------------+----------------------+
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| SYSTICK | on-chip | system clock |
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+--------------+------------+----------------------+
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The kernel currently does not support other hardware features on this platform.
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Interrupt Controller
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====================
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Refer to the :ref:`fsl_frdm_k64f`.
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.. note::
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Unlike the fsl_frdm_k64 board configuration, the qemu_cortex_m3
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board configuration sets option :option:`NUM_IRQ_PRIO_BITS` to '3'.
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System Clock
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============
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The qemu_cortex_m3 board configuration uses a system
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clock frequency of 12 MHz.
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Serial Port
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===========
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The qemu_cortex_m3 board configuration uses a single
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serial communication channel with the CPU's UART0.
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Known Problems or Limitations
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*****************************
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The following platform features are unsupported:
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* Memory protection through optional MPU.
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However, using a XIP kernel effectively provides
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TEXT/RODATA write protection in ROM.
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* SRAM at addresses 0x1FFF0000-0x1FFFFFFF
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* Writing to the hardware's flash memory
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Bibliography
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************
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1. The Definitive Guide to the ARM Cortex-M3,
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Second Edition by Joseph Yiu (ISBN 978-0-12-382090-7)
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2. ARMv7-M Architecture Technical Reference Manual
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(ARM DDI 0403D ID021310)
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3. Procedure Call Standard for the ARM Architecture
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(ARM IHI 0042E, current through ABI release 2.09,
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2012/11/30)
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4. Cortex-M3 Revision r2p1 Technical Reference Manual
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(ARM DDI 0337I ID072410)
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5. Cortex-M3 Devices Generic User Guide
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(ARM DUI 0052A ID121610)
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