Andrzej Głąbek fd07675574 drivers: pinctrl_nrf: Use S0D1 drive by default for TWI/TWIM pins ... The default S0S1 drive setting is not suitable for TWI/TWIM pins. Override it with S0D1 as for some SoCs (e.g. nRF52833) without this the peripheral will not work properly. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>		2022-07-05 13:52:19 +02:00
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arc/synopsys	dts: add reg-shift property to all ns16550 devices	2022-06-15 16:59:02 -05:00
arm	dts: stm32: Populate "st,stm32h7-spi" compatible when required	2022-07-04 14:23:34 +00:00
arm64	dts: arm64: intel: Enable Arm Timer for Intel Agilex SoC FPGA	2022-06-27 08:52:01 -05:00
bindings	drivers: pinctrl_nrf: Use S0D1 drive by default for TWI/TWIM pins	2022-07-05 13:52:19 +02:00
common	…
nios2/intel	dts: add reg-shift property to all ns16550 devices	2022-06-15 16:59:02 -05:00
posix	…
riscv	dts: riscv: add #address-cells to all interrupt controllers	2022-07-04 14:39:43 -04:00
sparc/gaisler	dts: sparc: gaisler: Move SoC devicetree includes under a vendor dir	2022-05-09 17:54:48 -04:00
x86/intel	dts: x86: intel: ia32: fix uart reg-shift	2022-06-17 10:45:28 -05:00
xtensa	dts: esp32: full ledc configuration in binding	2022-06-29 14:48:25 +00:00
Kconfig	drivers: gpio: remove unused HAS_DTS_GPIO Kconfig symbol	2022-06-10 09:47:31 +02:00
binding-template.yaml	…