214 lines
6.0 KiB
C
214 lines
6.0 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include "soc.h"
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#include <soc/rtc_cntl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <drivers/interrupt_controller/intc_esp32.h>
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#include <xtensa/config/core-isa.h>
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#include <xtensa/corebits.h>
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#include <kernel_structs.h>
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#include <string.h>
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#include <toolchain/gcc.h>
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#include <zephyr/types.h>
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#include "esp_private/system_internal.h"
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#include "esp32/rom/cache.h"
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#include "hal/soc_ll.h"
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#include "soc/cpu.h"
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#include "soc/gpio_periph.h"
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#include "esp_spi_flash.h"
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#include "esp_err.h"
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#include "esp32/spiram.h"
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#include "sys/printk.h"
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extern void z_cstart(void);
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/*
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* This is written in C rather than assembly since, during the port bring up,
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* Zephyr is being booted by the Espressif bootloader. With it, the C stack
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* is already set up.
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*/
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void __attribute__((section(".iram1"))) __start(void)
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{
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volatile uint32_t *wdt_rtc_protect = (uint32_t *)RTC_CNTL_WDTWPROTECT_REG;
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volatile uint32_t *wdt_rtc_reg = (uint32_t *)RTC_CNTL_WDTCONFIG0_REG;
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volatile uint32_t *app_cpu_config_reg = (uint32_t *)DPORT_APPCPU_CTRL_B_REG;
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extern uint32_t _init_start;
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extern uint32_t _bss_start;
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extern uint32_t _bss_end;
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/* Move the exception vector table to IRAM. */
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__asm__ __volatile__ (
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"wsr %0, vecbase"
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:
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: "r"(&_init_start));
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/* Zero out BSS. Clobber _bss_start to avoid memset() elision. */
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(void)memset(&_bss_start, 0,
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(&_bss_end - &_bss_start) * sizeof(_bss_start));
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__asm__ __volatile__ (
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""
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:
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: "g"(&_bss_start)
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: "memory");
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#if !CONFIG_BOOTLOADER_ESP_IDF
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/* The watchdog timer is enabled in the 1st stage (ROM) bootloader.
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* We're done booting, so disable it.
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* If 2nd stage bootloader from IDF is enabled, then that will take
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* care of this.
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*/
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volatile uint32_t *wdt_timg_protect = (uint32_t *)TIMG_WDTWPROTECT_REG(0);
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volatile uint32_t *wdt_timg_reg = (uint32_t *)TIMG_WDTCONFIG0_REG(0);
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*wdt_rtc_protect = RTC_CNTL_WDT_WKEY_VALUE;
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*wdt_rtc_reg &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
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*wdt_rtc_protect = 0;
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*wdt_timg_protect = TIMG_WDT_WKEY_VALUE;
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*wdt_timg_reg &= ~TIMG_WDT_FLASHBOOT_MOD_EN;
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*wdt_timg_protect = 0;
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#endif
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/* Disable normal interrupts. */
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__asm__ __volatile__ (
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"wsr %0, PS"
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:
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: "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
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/* Disable CPU1 while we figure out how to have SMP in Zephyr. */
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*app_cpu_config_reg &= ~DPORT_APPCPU_CLKGATE_EN;
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/* Initialize the architecture CPU pointer. Some of the
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* initialization code wants a valid _current before
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* arch_kernel_init() is invoked.
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*/
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__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
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#if CONFIG_BOOTLOADER_ESP_IDF
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/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
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* related issues in application. Hence disable that as we are about to start
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* Zephyr environment.
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*/
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*wdt_rtc_protect = RTC_CNTL_WDT_WKEY_VALUE;
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*wdt_rtc_reg &= ~RTC_CNTL_WDT_EN;
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*wdt_rtc_protect = 0;
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#endif
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#if CONFIG_ESP_SPIRAM
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esp_err_t err = esp_spiram_init();
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if (err != ESP_OK) {
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printk("Failed to Initialize SPIRAM, aborting.\n");
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abort();
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}
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esp_spiram_init_cache();
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if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) {
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printk("SPIRAM size is less than configured size, aborting.\n");
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abort();
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}
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#endif
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/* Scheduler is not started at this point. Hence, guard functions
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* must be initialized after esp_spiram_init_cache which internally
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* uses guard functions. Setting guard functions before SPIRAM
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* cache initialization will result in a crash.
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*/
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#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM
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spi_flash_guard_set(&g_flash_guard_default_ops);
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#endif
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esp_intr_initialize();
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/* Start Zephyr */
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z_cstart();
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CODE_UNREACHABLE;
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}
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/* Boot-time static default printk handler, possibly to be overridden later. */
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int IRAM_ATTR arch_printk_char_out(int c)
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{
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if (c == '\n') {
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esp32_rom_uart_tx_one_char('\r');
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}
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esp32_rom_uart_tx_one_char(c);
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return 0;
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}
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void sys_arch_reboot(int type)
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{
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esp_restart_noos();
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}
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void IRAM_ATTR esp_restart_noos(void)
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{
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/* Disable interrupts */
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z_xt_ints_off(0xFFFFFFFF);
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const uint32_t core_id = cpu_hal_get_core_id();
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const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
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soc_ll_reset_core(other_core_id);
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soc_ll_stall_core(other_core_id);
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/* Flush any data left in UART FIFOs */
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esp32_rom_uart_tx_wait_idle(0);
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esp32_rom_uart_tx_wait_idle(1);
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esp32_rom_uart_tx_wait_idle(2);
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/* Disable cache */
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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/* 2nd stage bootloader reconfigures SPI flash signals. */
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/* Reset them to the defaults expected by ROM */
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WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
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/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
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DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
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DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
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DPORT_BT_RST | DPORT_BTMAC_RST |
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DPORT_SDIO_RST | DPORT_SDIO_HOST_RST |
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DPORT_EMAC_RST | DPORT_MACPWR_RST |
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DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
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DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
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/* Reset timer/spi/uart */
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DPORT_SET_PERI_REG_MASK(
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DPORT_PERIP_RST_EN_REG,
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/* UART TX FIFO cannot be reset correctly on ESP32, */
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/* so reset the UART memory by DPORT here. */
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST |
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DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
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DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
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/* Clear entry point for APP CPU */
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DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
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/* Reset CPUs */
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if (core_id == 0) {
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/* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */
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soc_ll_reset_core(1);
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soc_ll_reset_core(0);
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} else {
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/* Running on APP CPU: need to reset PRO CPU and unstall it, */
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/* then reset APP CPU */
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soc_ll_reset_core(0);
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soc_ll_stall_core(0);
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soc_ll_reset_core(1);
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}
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while (true) {
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;
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}
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}
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