54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32H5 processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_icache.h>
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#include <zephyr/logging/log.h>
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#include <cmsis_core.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32h5_init(void)
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{
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/* Enable instruction cache in 1-way (direct mapped cache) */
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LL_ICACHE_SetMode(LL_ICACHE_1WAY);
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LL_ICACHE_Enable();
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 32 MHz from HSI with a HSIDIV = 2 */
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SystemCoreClock = 32000000;
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#if defined(PWR_UCPDR_UCPD_DBDIS)
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if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) ||
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!IS_ENABLED(CONFIG_USB_DEVICE_DRIVER)) {
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/* Disable USB Type-C dead battery pull-down behavior */
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LL_PWR_DisableUCPDDeadBattery();
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}
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#endif /* PWR_UCPDR_UCPD_DBDIS */
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return 0;
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}
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SYS_INIT(stm32h5_init, PRE_KERNEL_1, 0);
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