4ea52bdd12
This patch updates the power status register bitfield definitions in the power management header for the Intel ADSP ACE 2.0 LNL platform. Modifications include: - Adjusting the 'ioxpgs' field from 4 bits to 2 bits. - Adding a 'rsvd11' field with 2 bits to reflect reserved space. - Changing the 'mlpgs' field from 2 bits to 1 bit. - Updating the 'rsvd14' field from 1 bit to 2 bits for alignment. These changes ensure that the power status register bitfields match the latest hardware specification for the ACE 2.0 LNL SoC, which is crucial for accurate power domain status monitoring. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com> |
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| .. | ||
| alder_lake | ||
| apollo_lake | ||
| atom | ||
| elkhart_lake | ||
| intel_adsp | ||
| intel_ish | ||
| intel_niosv | ||
| intel_socfpga | ||
| intel_socfpga_std | ||
| lakemont | ||
| raptor_lake | ||