158 lines
3.6 KiB
Plaintext
158 lines
3.6 KiB
Plaintext
/*
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* Copyright (c) 2019 Argentum Systems Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f1/stm32f1.dtsi>
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/ {
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clocks {
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/delete-node/ pll;
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32f105-pll-clock";
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status = "disabled";
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};
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pll2: pll2 {
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#clock-cells = <0>;
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compatible = "st,stm32f105-pll2-clock";
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clocks = <&clk_hse>;
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status = "disabled";
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};
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};
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soc {
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compatible = "st,stm32f105", "st,stm32f1", "simple-bus";
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flash-controller@40022000 {
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flash0: flash@8000000 {
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erase-block-size = <DT_SIZE_K(2)>;
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};
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};
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can1: can@40006400 {
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compatible = "st,stm32-bxcan";
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reg = <0x40006400 0x400>;
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interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
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interrupt-names = "TX", "RX0", "RX1", "SCE";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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status = "disabled";
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};
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can2: can@40006800 {
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compatible = "st,stm32-bxcan";
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reg = <0x40006800 0x400>;
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interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
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interrupt-names = "TX", "RX0", "RX1", "SCE";
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/* also enabling clock for can1 (master instance) */
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
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status = "disabled";
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1, 19U)>;
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interrupts = <52 0>;
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status = "disabled";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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resets = <&rctl STM32_RESET(APB1, 20U)>;
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interrupts = <53 0>;
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status = "disabled";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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status = "disabled";
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};
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timers5: timers@40000c00 {
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compatible = "st,stm32-timers";
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reg = <0x40000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
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resets = <&rctl STM32_RESET(APB1, 3U)>;
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interrupts = <50 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
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resets = <&rctl STM32_RESET(APB1, 4U)>;
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interrupts = <54 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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resets = <&rctl STM32_RESET(APB1, 5U)>;
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interrupts = <55 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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};
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usbotg_fs: usb@50000000 {
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compatible = "st,stm32-otgfs";
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reg = <0x50000000 0x40000>;
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interrupts = <67 0>;
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interrupt-names = "otgfs";
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num-bidir-endpoints = <4>;
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ram-size = <1280>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00001000>;
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phys = <&otgfs_phy>;
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status = "disabled";
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};
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};
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otgfs_phy: otgfs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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