136 lines
3.0 KiB
Plaintext
136 lines
3.0 KiB
Plaintext
/* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2020 Google, LLC
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*
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* SoC device tree include for STM32F103xG SoCs
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* where 'x' is replaced for specific SoCs like {R,V,Z}
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*/
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#include <mem.h>
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#include <st/f1/stm32f103Xe.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(96)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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/* Note that there are actually two banks of
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* flash (512KB each) and two flash controllers.
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* This matters if you're doing in-application
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* flash programming and you need the
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* read-while-write capabilities, but is
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* otherwise a non-issue.
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*/
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reg = <0x08000000 DT_SIZE_K(1024)>;
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erase-block-size = <DT_SIZE_K(2)>;
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};
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};
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timers9: timers@40014c00 {
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compatible = "st,stm32-timers";
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reg = <0x40014c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
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resets = <&rctl STM32_RESET(APB2, 19U)>;
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/* Shared with TIM1_BRK */
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interrupts = <24 0>;
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers10: timers@40015000 {
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compatible = "st,stm32-timers";
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reg = <0x40015000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
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resets = <&rctl STM32_RESET(APB2, 20U)>;
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/* Shared with TIM1_UP */
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interrupts = <25 0>;
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers11: timers@40015400 {
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compatible = "st,stm32-timers";
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reg = <0x40015400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
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resets = <&rctl STM32_RESET(APB2, 21U)>;
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/* Shared with TIM1_TRG_COM */
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interrupts = <26 0>;
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers12: timers@40001800 {
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compatible = "st,stm32-timers";
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reg = <0x40001800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
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resets = <&rctl STM32_RESET(APB1, 6U)>;
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/* Shared with TIM8_BRK */
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interrupts = <43 0>;
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers13: timers@40001c00 {
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compatible = "st,stm32-timers";
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reg = <0x40001c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
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resets = <&rctl STM32_RESET(APB1, 7U)>;
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/* Shared with TIM8_UP */
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interrupts = <44 0>;
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers14: timers@40002000 {
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
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resets = <&rctl STM32_RESET(APB1, 8U)>;
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/* Shared with TIM8_TRG_COM */
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interrupts = <45 0>;
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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};
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};
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