167 lines
3.9 KiB
Plaintext
167 lines
3.9 KiB
Plaintext
/*
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* Copyright (c) 2017 I-SENSE group of ICCS
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*
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* SoC device tree include for STM32F103xC SoCs
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* where 'x' is replaced for specific SoCs like {R,V,Z}
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/f1/stm32f103Xb.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(48)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(256)>;
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erase-block-size = <DT_SIZE_K(2)>;
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};
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1, 19U)>;
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interrupts = <52 0>;
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status = "disabled";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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resets = <&rctl STM32_RESET(APB1, 20U)>;
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interrupts = <53 0>;
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status = "disabled";
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};
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timers5: timers@40000c00 {
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compatible = "st,stm32-timers";
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reg = <0x40000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
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resets = <&rctl STM32_RESET(APB1, 3U)>;
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interrupts = <50 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
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resets = <&rctl STM32_RESET(APB1, 4U)>;
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interrupts = <54 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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resets = <&rctl STM32_RESET(APB1, 5U)>;
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interrupts = <55 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0X40003c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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status = "disabled";
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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pinctrl: pin-controller@40010800 {
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reg = <0x40010800 0x2000>;
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gpiof: gpio@40011c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40011c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
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};
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gpiog: gpio@40012000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40012000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
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};
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};
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adc2: adc@40012800 {
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compatible = "st,stm32-adc";
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reg = <0x40012800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
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/* Shares vector with ADC1 */
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interrupts = <18 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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adc3: adc@40013c00 {
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compatible = "st,stm32-adc";
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reg = <0x40013c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
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interrupts = <47 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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timers8: timers@40013400 {
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compatible = "st,stm32-timers";
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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resets = <&rctl STM32_RESET(APB2, 13U)>;
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interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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dma2: dma@40020400 {
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compatible = "st,stm32-dma-v2bis";
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#dma-cells = <2>;
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reg = <0x40020400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
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interrupts = < 56 0 57 0 58 0 59 0 60 0>;
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status = "disabled";
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};
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};
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};
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