zephyr/dts/arm/nxp/nxp_kl25z.dtsi

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/* SPDX-License-Identifier: Apache-2.0 */
#include <mem.h>
#include "armv6-m.dtsi"
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/clock/kinetis_sim.h>
#include <zephyr/dt-bindings/clock/kinetis_mcg.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
/ {
chosen {
zephyr,flash-controller = &ftfa;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
};
};
sram0: memory@1FFFF000 {
compatible = "mmio-sram";
reg = <0x1FFFF000 DT_SIZE_K(16)>;
};
/* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl";
status = "okay";
};
soc {
ftfa: flash-controller@40020000 {
compatible = "nxp,kinetis-ftfa";
reg = <0x40020000 0x14>;
interrupts = <5 0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
reg = <0 DT_SIZE_K(128)>;
erase-block-size = <1024>;
write-block-size = <4>;
};
};
mcg: clock-controller@40064000 {
compatible = "nxp,kinetis-mcg";
reg = <0x40064000 0xd>;
#clock-cells = <1>;
};
i2c0: i2c@40066000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40066000 0x1000>;
interrupts = <8 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
status = "disabled";
};
i2c1: i2c@40067000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40067000 0x1000>;
interrupts = <9 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
status = "disabled";
};
sim: sim@40047000 {
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
#clock-cells = <3>;
core_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <2>;
#clock-cells = <0>;
};
flash_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <2>;
#clock-cells = <0>;
};
};
uart0: uart@4006a000 {
compatible = "nxp,kinetis-lpsci";
reg = <0x4006a000 0xc>;
interrupts = <12 0>;
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
status = "disabled";
};
adc0: adc@4003b000{
compatible = "nxp,kinetis-adc16";
reg = <0x4003b000 0x70>;
interrupts = <15 0>;
status = "disabled";
#io-channel-cells = <1>;
};
porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
};
portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
};
portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
};
portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
};
porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
};
gpioa: gpio@400ff000 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff000 0x40>;
interrupts = <30 2>;
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&porta>;
};
gpiob: gpio@400ff040 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff040 0x40>;
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portb>;
};
gpioc: gpio@400ff080 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff080 0x40>;
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portc>;
};
gpiod: gpio@400ff0c0 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff0c0 0x40>;
interrupts = <31 2>;
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portd>;
};
gpioe: gpio@400ff100 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff100 0x40>;
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&porte>;
};
usbotg: usbd@40072000 {
compatible = "nxp,kinetis-usbd";
reg = <0x40072000 0x1000>;
interrupts = <24 1>;
interrupt-names = "usb_otg";
num-bidir-endpoints = <16>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};