105 lines
3.4 KiB
C
105 lines
3.4 KiB
C
/* W5500 Stand-alone Ethernet Controller with SPI
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*
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* Copyright (c) 2020 Linumiz
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* Author: Parthiban Nallathambi <parthiban@linumiz.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/spi.h>
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#ifndef _W5500_
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#define _W5500_
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/*
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* W5500 common registers
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*/
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#define W5500_COMMON_REGS 0x0000
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#define W5500_MR 0x0000 /* Mode Register */
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#define W5500_GW 0x0001
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#define MR_RST 0x80 /* S/W reset */
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#define MR_PB 0x10 /* Ping block */
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#define MR_AI 0x02 /* Address Auto-Increment */
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#define MR_IND 0x01 /* Indirect mode */
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#define W5500_SHAR 0x0009 /* Source MAC address */
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#define W5500_IR 0x0015 /* Interrupt Register */
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#define W5500_COMMON_REGS_LEN 0x0040
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#define W5500_Sn_MR 0x0000 /* Sn Mode Register */
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#define W5500_Sn_CR 0x0001 /* Sn Command Register */
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#define W5500_Sn_IR 0x0002 /* Sn Interrupt Register */
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#define W5500_Sn_SR 0x0003 /* Sn Status Register */
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#define W5500_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */
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#define W5500_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */
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#define W5500_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */
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#define W5500_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */
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#define W5500_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */
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#define W5500_S0_REGS 0x10000
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#define W5500_S0_MR (W5500_S0_REGS + W5500_Sn_MR)
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#define S0_MR_MACRAW 0x04 /* MAC RAW mode */
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#define S0_MR_MF 0x40 /* MAC Filter for W5500 */
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#define W5500_S0_CR (W5500_S0_REGS + W5500_Sn_CR)
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#define S0_CR_OPEN 0x01 /* OPEN command */
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#define S0_CR_CLOSE 0x10 /* CLOSE command */
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#define S0_CR_SEND 0x20 /* SEND command */
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#define S0_CR_RECV 0x40 /* RECV command */
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#define W5500_S0_IR (W5500_S0_REGS + W5500_Sn_IR)
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#define S0_IR_SENDOK 0x10 /* complete sending */
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#define S0_IR_RECV 0x04 /* receiving data */
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#define W5500_S0_SR (W5500_S0_REGS + W5500_Sn_SR)
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#define S0_SR_MACRAW 0x42 /* mac raw mode */
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#define W5500_S0_TX_FSR (W5500_S0_REGS + W5500_Sn_TX_FSR)
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#define W5500_S0_TX_RD (W5500_S0_REGS + W5500_Sn_TX_RD)
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#define W5500_S0_TX_WR (W5500_S0_REGS + W5500_Sn_TX_WR)
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#define W5500_S0_RX_RSR (W5500_S0_REGS + W5500_Sn_RX_RSR)
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#define W5500_S0_RX_RD (W5500_S0_REGS + W5500_Sn_RX_RD)
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#define W5500_S0_IMR (W5500_S0_REGS + W5500_Sn_IMR)
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#define W5500_S0_MR_MF 7 /* MAC Filter for W5500 */
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#define W5500_Sn_REGS_LEN 0x0040
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#define W5500_SIMR 0x0018 /* Socket Interrupt Mask Register */
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#define IR_S0 0x01
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#define RTR_DEFAULT 2000
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#define W5500_RTR 0x0019 /* Retry Time-value Register */
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#define W5500_Sn_RXMEM_SIZE(n) \
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(0x1001e + (n) * 0x40000) /* Sn RX Memory Size */
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#define W5500_Sn_TXMEM_SIZE(n) \
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(0x1001f + (n) * 0x40000) /* Sn TX Memory Size */
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#define W5500_Sn_TX_MEM_START 0x20000
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#define W5500_TX_MEM_SIZE 0x04000
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#define W5500_Sn_RX_MEM_START 0x30000
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#define W5500_RX_MEM_SIZE 0x04000
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/* Delay for PHY write/read operations (25.6 us) */
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#define W5500_PHY_ACCESS_DELAY 26U
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struct w5500_config {
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struct spi_dt_spec spi;
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struct gpio_dt_spec interrupt;
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struct gpio_dt_spec reset;
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void (*config_func)(void);
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uint8_t full_duplex;
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int32_t timeout;
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};
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struct w5500_runtime {
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struct net_if *iface;
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K_KERNEL_STACK_MEMBER(thread_stack,
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CONFIG_ETH_W5500_RX_THREAD_STACK_SIZE);
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struct k_thread thread;
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uint8_t mac_addr[6];
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struct gpio_callback gpio_cb;
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struct k_sem tx_sem;
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struct k_sem int_sem;
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void (*generate_mac)(uint8_t *mac);
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uint8_t buf[NET_ETH_MAX_FRAME_SIZE];
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};
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#endif /*_W5500_*/
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