233 lines
7.5 KiB
C
233 lines
7.5 KiB
C
/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/drivers/can.h>
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#include <zephyr/drivers/can/can_mcan.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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LOG_MODULE_REGISTER(can_mcux_mcan, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT nxp_lpc_mcan
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/* Message RAM Base Address register */
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#define MCUX_MCAN_MRBA 0x200
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#define MCUX_MCAN_MRBA_BA GENMASK(31, 16)
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struct mcux_mcan_config {
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mm_reg_t base;
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mem_addr_t mram;
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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void (*irq_config_func)(const struct device *dev);
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const struct pinctrl_dev_config *pincfg;
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};
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static int mcux_mcan_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct mcux_mcan_config *mcux_config = mcan_config->custom;
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return can_mcan_sys_read_reg(mcux_config->base, reg, val);
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}
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static int mcux_mcan_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct mcux_mcan_config *mcux_config = mcan_config->custom;
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return can_mcan_sys_write_reg(mcux_config->base, reg, val);
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}
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static int mcux_mcan_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct mcux_mcan_config *mcux_config = mcan_config->custom;
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return can_mcan_sys_read_mram(mcux_config->mram, offset, dst, len);
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}
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static int mcux_mcan_write_mram(const struct device *dev, uint16_t offset, const void *src,
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size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct mcux_mcan_config *mcux_config = mcan_config->custom;
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return can_mcan_sys_write_mram(mcux_config->mram, offset, src, len);
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}
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static int mcux_mcan_clear_mram(const struct device *dev, uint16_t offset, size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct mcux_mcan_config *mcux_config = mcan_config->custom;
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return can_mcan_sys_clear_mram(mcux_config->mram, offset, len);
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}
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static int mcux_mcan_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct mcux_mcan_config *mcux_config = mcan_config->custom;
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return clock_control_get_rate(mcux_config->clock_dev, mcux_config->clock_subsys,
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rate);
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}
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static int mcux_mcan_init(const struct device *dev)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct mcux_mcan_config *mcux_config = mcan_config->custom;
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const uintptr_t mrba = mcux_config->mram & MCUX_MCAN_MRBA_BA;
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int err;
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if (!device_is_ready(mcux_config->clock_dev)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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err = pinctrl_apply_state(mcux_config->pincfg, PINCTRL_STATE_DEFAULT);
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if (err) {
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return err;
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}
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err = clock_control_on(mcux_config->clock_dev, mcux_config->clock_subsys);
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if (err) {
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LOG_ERR("failed to enable clock (err %d)", err);
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return -EINVAL;
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}
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err = can_mcan_write_reg(dev, MCUX_MCAN_MRBA, (uint32_t)mrba);
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if (err != 0) {
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return -EIO;
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}
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err = can_mcan_configure_mram(dev, mrba, mcux_config->mram);
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if (err != 0) {
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return -EIO;
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}
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err = can_mcan_init(dev);
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if (err) {
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LOG_ERR("failed to initialize mcan (err %d)", err);
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return err;
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}
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mcux_config->irq_config_func(dev);
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return 0;
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}
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static const struct can_driver_api mcux_mcan_driver_api = {
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.get_capabilities = can_mcan_get_capabilities,
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.start = can_mcan_start,
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.stop = can_mcan_stop,
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.set_mode = can_mcan_set_mode,
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.set_timing = can_mcan_set_timing,
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.send = can_mcan_send,
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.add_rx_filter = can_mcan_add_rx_filter,
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.remove_rx_filter = can_mcan_remove_rx_filter,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_mcan_recover,
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#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
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.get_state = can_mcan_get_state,
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.set_state_change_callback = can_mcan_set_state_change_callback,
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.get_core_clock = mcux_mcan_get_core_clock,
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.get_max_filters = can_mcan_get_max_filters,
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/*
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* MCUX MCAN timing limits are specified in the "Nominal bit timing and
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* prescaler register (NBTP)" table in the SoC reference manual.
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*
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* Note that the values here are the "physical" timing limits, whereas
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* the register field limits are physical values minus 1 (which is
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* handled by the register assignments in the common MCAN driver code).
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*
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* Beware that at least some SoC reference manuals contain a bug
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* regarding the minimum values for nominal phase segments. Valid
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* register values are 1 and up.
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*/
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.timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
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.timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
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#ifdef CONFIG_CAN_FD_MODE
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.set_timing_data = can_mcan_set_timing_data,
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/*
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* MCUX MCAN data timing limits are specified in the "Data bit timing
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* and prescaler register (DBTP)" table in the SoC reference manual.
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*
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* Note that the values here are the "physical" timing limits, whereas
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* the register field limits are physical values minus 1 (which is
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* handled by the register assignments in the common MCAN driver code).
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*
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* Beware that at least some SoC reference manuals contain a bug
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* regarding the maximum value for data phase segment 2. Valid register
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* values are 0 to 31.
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*/
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.timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
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.timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
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#endif /* CONFIG_CAN_FD_MODE */
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};
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static const struct can_mcan_ops mcux_mcan_ops = {
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.read_reg = mcux_mcan_read_reg,
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.write_reg = mcux_mcan_write_reg,
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.read_mram = mcux_mcan_read_mram,
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.write_mram = mcux_mcan_write_mram,
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.clear_mram = mcux_mcan_clear_mram,
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};
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#define MCUX_MCAN_INIT(n) \
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CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(n); \
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static void mcux_mcan_irq_config_##n(const struct device *dev); \
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\
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CAN_MCAN_DT_INST_CALLBACKS_DEFINE(n, mcux_mcan_cbs_##n); \
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CAN_MCAN_DT_INST_MRAM_DEFINE(n, mcux_mcan_mram_##n); \
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\
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static const struct mcux_mcan_config mcux_mcan_config_##n = { \
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.base = CAN_MCAN_DT_INST_MCAN_ADDR(n), \
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.mram = (mem_addr_t)POINTER_TO_UINT(&mcux_mcan_mram_##n), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_subsys = (clock_control_subsys_t) \
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DT_INST_CLOCKS_CELL(n, name), \
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.irq_config_func = mcux_mcan_irq_config_##n, \
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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}; \
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\
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static const struct can_mcan_config can_mcan_config_##n = \
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CAN_MCAN_DT_CONFIG_INST_GET(n, &mcux_mcan_config_##n, \
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&mcux_mcan_ops, \
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&mcux_mcan_cbs_##n); \
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\
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static struct can_mcan_data can_mcan_data_##n = \
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CAN_MCAN_DATA_INITIALIZER(NULL); \
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\
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CAN_DEVICE_DT_INST_DEFINE(n, mcux_mcan_init, NULL, \
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&can_mcan_data_##n, \
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&can_mcan_config_##n, \
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POST_KERNEL, \
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CONFIG_CAN_INIT_PRIORITY, \
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&mcux_mcan_driver_api); \
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\
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static void mcux_mcan_irq_config_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, int0, irq), \
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DT_INST_IRQ_BY_NAME(n, int0, priority), \
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can_mcan_line_0_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(n, int0, irq)); \
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\
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, int1, irq), \
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DT_INST_IRQ_BY_NAME(n, int1, priority), \
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can_mcan_line_1_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(n, int1, irq)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(MCUX_MCAN_INIT)
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