183 lines
6.9 KiB
C
183 lines
6.9 KiB
C
/*
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* Copyright (c) 2017 PHYTEC Messtechnik GmbH
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*
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* Portions of this file are derived from ieee802154_cc2520.h that is
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_
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#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_
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#include <linker/sections.h>
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#include <sys/atomic.h>
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#include <drivers/spi.h>
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/* Runtime context structure
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***************************
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*/
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struct mcr20a_context {
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struct net_if *iface;
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/**************************/
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struct device *irq_gpio;
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struct device *reset_gpio;
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struct gpio_callback irqb_cb;
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struct device *spi;
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struct spi_config spi_cfg;
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#if defined(DT_NXP_MCR20A_0_CS_GPIOS_CONTROLLER)
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struct spi_cs_control cs_ctrl;
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#endif
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u8_t mac_addr[8];
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struct k_mutex phy_mutex;
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struct k_sem isr_sem;
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/*********TX + CCA*********/
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struct k_sem seq_sync;
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atomic_t seq_retval;
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/************RX************/
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K_THREAD_STACK_MEMBER(mcr20a_rx_stack,
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CONFIG_IEEE802154_MCR20A_RX_STACK_SIZE);
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struct k_thread mcr20a_rx_thread;
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};
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#include "ieee802154_mcr20a_regs.h"
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u8_t z_mcr20a_read_reg(struct mcr20a_context *dev, bool dreg, u8_t addr);
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bool z_mcr20a_write_reg(struct mcr20a_context *dev, bool dreg, u8_t addr,
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u8_t value);
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bool z_mcr20a_write_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
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u8_t *data_buf, u8_t len);
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bool z_mcr20a_read_burst(struct mcr20a_context *dev, bool dreg, u16_t addr,
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u8_t *data_buf, u8_t len);
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#define DEFINE_REG_READ(__reg_name, __reg_addr, __dreg) \
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static inline u8_t read_reg_##__reg_name(struct mcr20a_context *dev) \
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{ \
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return z_mcr20a_read_reg(dev, __dreg, __reg_addr); \
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}
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#define DEFINE_REG_WRITE(__reg_name, __reg_addr, __dreg) \
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static inline bool write_reg_##__reg_name(struct mcr20a_context *dev, \
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u8_t value) \
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{ \
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return z_mcr20a_write_reg(dev, __dreg, __reg_addr, value); \
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}
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#define DEFINE_DREG_READ(__reg_name, __reg_addr) \
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DEFINE_REG_READ(__reg_name, __reg_addr, true)
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#define DEFINE_DREG_WRITE(__reg_name, __reg_addr) \
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DEFINE_REG_WRITE(__reg_name, __reg_addr, true)
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#define DEFINE_IREG_READ(__reg_name, __reg_addr) \
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DEFINE_REG_READ(__reg_name, __reg_addr, false)
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#define DEFINE_IREG_WRITE(__reg_name, __reg_addr) \
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DEFINE_REG_WRITE(__reg_name, __reg_addr, false)
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DEFINE_DREG_READ(irqsts1, MCR20A_IRQSTS1)
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DEFINE_DREG_READ(irqsts2, MCR20A_IRQSTS2)
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DEFINE_DREG_READ(irqsts3, MCR20A_IRQSTS3)
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DEFINE_DREG_READ(phy_ctrl1, MCR20A_PHY_CTRL1)
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DEFINE_DREG_READ(phy_ctrl2, MCR20A_PHY_CTRL2)
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DEFINE_DREG_READ(phy_ctrl3, MCR20A_PHY_CTRL3)
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DEFINE_DREG_READ(rx_frm_len, MCR20A_RX_FRM_LEN)
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DEFINE_DREG_READ(phy_ctrl4, MCR20A_PHY_CTRL4)
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DEFINE_DREG_READ(src_ctrl, MCR20A_SRC_CTRL)
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DEFINE_DREG_READ(cca1_ed_fnl, MCR20A_CCA1_ED_FNL)
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DEFINE_DREG_READ(pll_int0, MCR20A_PLL_INT0)
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DEFINE_DREG_READ(pa_pwr, MCR20A_PA_PWR)
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DEFINE_DREG_READ(seq_state, MCR20A_SEQ_STATE)
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DEFINE_DREG_READ(lqi_value, MCR20A_LQI_VALUE)
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DEFINE_DREG_READ(rssi_cca_cnt, MCR20A_RSSI_CCA_CNT)
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DEFINE_DREG_READ(asm_ctrl1, MCR20A_ASM_CTRL1)
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DEFINE_DREG_READ(asm_ctrl2, MCR20A_ASM_CTRL2)
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DEFINE_DREG_READ(overwrite_ver, MCR20A_OVERWRITE_VER)
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DEFINE_DREG_READ(clk_out_ctrl, MCR20A_CLK_OUT_CTRL)
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DEFINE_DREG_READ(pwr_modes, MCR20A_PWR_MODES)
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DEFINE_DREG_WRITE(irqsts1, MCR20A_IRQSTS1)
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DEFINE_DREG_WRITE(irqsts2, MCR20A_IRQSTS2)
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DEFINE_DREG_WRITE(irqsts3, MCR20A_IRQSTS3)
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DEFINE_DREG_WRITE(phy_ctrl1, MCR20A_PHY_CTRL1)
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DEFINE_DREG_WRITE(phy_ctrl2, MCR20A_PHY_CTRL2)
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DEFINE_DREG_WRITE(phy_ctrl3, MCR20A_PHY_CTRL3)
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DEFINE_DREG_WRITE(phy_ctrl4, MCR20A_PHY_CTRL4)
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DEFINE_DREG_WRITE(src_ctrl, MCR20A_SRC_CTRL)
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DEFINE_DREG_WRITE(pll_int0, MCR20A_PLL_INT0)
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DEFINE_DREG_WRITE(pa_pwr, MCR20A_PA_PWR)
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DEFINE_DREG_WRITE(asm_ctrl1, MCR20A_ASM_CTRL1)
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DEFINE_DREG_WRITE(asm_ctrl2, MCR20A_ASM_CTRL2)
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DEFINE_DREG_WRITE(overwrite_ver, MCR20A_OVERWRITE_VER)
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DEFINE_DREG_WRITE(clk_out_ctrl, MCR20A_CLK_OUT_CTRL)
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DEFINE_DREG_WRITE(pwr_modes, MCR20A_PWR_MODES)
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DEFINE_IREG_READ(part_id, MCR20A_PART_ID)
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DEFINE_IREG_READ(rx_frame_filter, MCR20A_RX_FRAME_FILTER)
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DEFINE_IREG_READ(cca1_thresh, MCR20A_CCA1_THRESH)
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DEFINE_IREG_READ(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP)
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DEFINE_IREG_READ(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP)
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DEFINE_IREG_READ(cca_ctrl, MCR20A_CCA_CTRL)
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DEFINE_IREG_READ(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS)
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DEFINE_IREG_READ(cca2_thresh, MCR20A_CCA2_THRESH)
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DEFINE_IREG_READ(tmr_prescale, MCR20A_TMR_PRESCALE)
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DEFINE_IREG_READ(rx_byte_count, MCR20A_RX_BYTE_COUNT)
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DEFINE_IREG_READ(rx_wtr_mark, MCR20A_RX_WTR_MARK)
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DEFINE_IREG_WRITE(part_id, MCR20A_PART_ID)
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DEFINE_IREG_WRITE(rx_frame_filter, MCR20A_RX_FRAME_FILTER)
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DEFINE_IREG_WRITE(cca1_thresh, MCR20A_CCA1_THRESH)
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DEFINE_IREG_WRITE(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP)
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DEFINE_IREG_WRITE(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP)
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DEFINE_IREG_WRITE(cca_ctrl, MCR20A_CCA_CTRL)
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DEFINE_IREG_WRITE(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS)
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DEFINE_IREG_WRITE(cca2_thresh, MCR20A_CCA2_THRESH)
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DEFINE_IREG_WRITE(tmr_prescale, MCR20A_TMR_PRESCALE)
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DEFINE_IREG_WRITE(rx_byte_count, MCR20A_RX_BYTE_COUNT)
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DEFINE_IREG_WRITE(rx_wtr_mark, MCR20A_RX_WTR_MARK)
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#define DEFINE_BITS_SET(__reg_name, __reg_addr, __nibble) \
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static inline u8_t set_bits_##__reg_name(u8_t value) \
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{ \
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value = (value << __reg_addr##__nibble##_SHIFT) & \
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__reg_addr##__nibble##_MASK; \
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return value; \
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}
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DEFINE_BITS_SET(phy_ctrl1_xcvseq, MCR20A_PHY_CTRL1, _XCVSEQ)
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DEFINE_BITS_SET(phy_ctrl4_ccatype, MCR20A_PHY_CTRL4, _CCATYPE)
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DEFINE_BITS_SET(pll_int0_val, MCR20A_PLL_INT0, _VAL)
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DEFINE_BITS_SET(pa_pwr_val, MCR20A_PA_PWR, _VAL)
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DEFINE_BITS_SET(tmr_prescale, MCR20A_TMR_PRESCALE, _VAL)
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DEFINE_BITS_SET(clk_out_div, MCR20A_CLK_OUT, _DIV)
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#define DEFINE_BURST_WRITE(__reg_addr, __addr, __sz, __dreg) \
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static inline bool write_burst_##__reg_addr( \
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struct mcr20a_context *dev, u8_t *buf) \
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{ \
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return z_mcr20a_write_burst(dev, __dreg, __addr, buf, __sz); \
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}
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#define DEFINE_BURST_READ(__reg_addr, __addr, __sz, __dreg) \
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static inline bool read_burst_##__reg_addr(struct mcr20a_context *dev, \
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u8_t *buf) \
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{ \
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return z_mcr20a_read_burst(dev, __dreg, __addr, buf, __sz); \
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}
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DEFINE_BURST_WRITE(t1cmp, MCR20A_T1CMP_LSB, 3, true)
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DEFINE_BURST_WRITE(t2cmp, MCR20A_T2CMP_LSB, 3, true)
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DEFINE_BURST_WRITE(t3cmp, MCR20A_T3CMP_LSB, 3, true)
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DEFINE_BURST_WRITE(t4cmp, MCR20A_T4CMP_LSB, 3, true)
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DEFINE_BURST_WRITE(t2primecmp, MCR20A_T2PRIMECMP_LSB, 2, true)
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DEFINE_BURST_WRITE(pll_int0, MCR20A_PLL_INT0, 3, true)
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DEFINE_BURST_WRITE(irqsts1_irqsts3, MCR20A_IRQSTS1, 3, true)
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DEFINE_BURST_WRITE(irqsts1_ctrl1, MCR20A_IRQSTS1, 4, true)
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DEFINE_BURST_WRITE(pan_id, MCR20A_MACPANID0_LSB, 2, false)
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DEFINE_BURST_WRITE(short_addr, MCR20A_MACSHORTADDRS0_LSB, 2, false)
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DEFINE_BURST_WRITE(ext_addr, MCR20A_MACLONGADDRS0_0, 8, false)
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DEFINE_BURST_READ(event_timer, MCR20A_EVENT_TIMER_LSB, 3, true)
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DEFINE_BURST_READ(irqsts1_ctrl4, MCR20A_IRQSTS1, 8, true)
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#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_ */
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