28 lines
435 B
Plaintext
28 lines
435 B
Plaintext
/*
|
|
* Copyright (c) 2018 Intel Corporation
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include <mem.h>
|
|
|
|
#define DT_SRAM_SIZE DT_SIZE_M(2048)
|
|
|
|
#include <apollo_lake.dtsi>
|
|
|
|
/ {
|
|
model = "up_squared";
|
|
compatible = "intel,apollo_lake";
|
|
|
|
chosen {
|
|
zephyr,sram = &sram0;
|
|
zephyr,console = &uart0;
|
|
zephyr,shell-uart = &uart0;
|
|
zephyr,bt-uart = &uart1;
|
|
zephyr,uart-pipe = &uart1;
|
|
zephyr,bt-mon-uart = &uart1;
|
|
};
|
|
};
|