49 lines
1.0 KiB
C
49 lines
1.0 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_
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#define ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_
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#include <zephyr/types.h>
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#include <device.h>
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/*
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* GIC Register Interface Base Addresses
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*/
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#define GIC_RDIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)
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#define GIC_GET_RDIST(cpuid) gic_rdists[cpuid]
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/* SGI base is at 64K offset from Redistributor */
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#define GICR_SGI_BASE_OFF 0x10000
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/* GICR registers offset from RD_base(n) */
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#define GICR_CTLR 0x0000
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#define GICR_IIDR 0x0004
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#define GICR_TYPER 0x0008
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#define GICR_STATUSR 0x0010
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#define GICR_WAKER 0x0014
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/* Register bit definations */
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/* GICD_CTLR Interrupt group definitions */
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#define GICD_CTLR_ENABLE_G0 0
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#define GICD_CTLR_ENABLE_G1NS 1
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#define GICD_CTLR_ENABLE_G1S 2
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/* GICD_CTLR Register write progress bit */
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#define GICD_CTLR_RWP 31
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/* GICR_CTLR */
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#define GICR_CTLR_RWP 3
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/* GICR_WAKER */
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#define GICR_WAKER_PS 1
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#define GICR_WAKER_CA 2
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#endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ */
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