49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2020 Linumiz
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* Author: Parthiban Nallathambi <parthiban@linumiz.com>
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*
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*/
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#include <xmc_scu.h>
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#include <zephyr/kernel.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#ifdef CONFIG_SOC_XMC4500
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#define PMU_FLASH_WS (0x3U)
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#elif CONFIG_SOC_XMC4700
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#define PMU_FLASH_WS (0x4U)
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#endif
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void soc_reset_hook(void)
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{
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uint32_t temp;
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/* unaligned trap bit is enabled on reset. disable it here and set later via */
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/* CONFIG_TRAP_UNALIGNED_ACCESS if needed. */
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SCB->CCR &= ~SCB_CCR_UNALIGN_TRP_Msk;
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/* setup flash wait state */
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temp = FLASH0->FCON;
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temp &= ~FLASH_FCON_WSPFLASH_Msk;
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temp |= PMU_FLASH_WS;
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FLASH0->FCON = temp;
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XMC_SCU_CLOCK_SetSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FPLL
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#ifdef CONFIG_PWM_XMC4XXX_CCU4
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| XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU
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#endif
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#ifdef CONFIG_PWM_XMC4XXX_CCU8
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| XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU
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#endif
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#ifdef CONFIG_ETH_XMC4XXX
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| XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_ETH
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#endif
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);
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/* configure PLL & system clock */
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SystemCoreClockSetup();
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}
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