264 lines
7.9 KiB
C
264 lines
7.9 KiB
C
/*
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* Copyright (c) 2019 Antmicro <www.antmicro.com>
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* Copyright (c) 2024 Vogl Electronic GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT litex_spi
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_litex);
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#include "spi_litex_common.h"
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#define POSITION_WORD_SIZE 8
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struct spi_litex_data {
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struct spi_context ctx;
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uint8_t dfs; /* dfs in bytes: 1,2,3 or 4 */
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};
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struct spi_litex_cfg {
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uint32_t control_addr;
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uint32_t status_addr;
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uint32_t mosi_addr;
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uint32_t miso_addr;
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uint32_t cs_addr;
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uint32_t loopback_addr;
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uint32_t clk_divider_addr;
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bool clk_divider_exists;
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int data_width;
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int max_cs;
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};
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static void spi_set_frequency(const struct device *dev, const struct spi_config *config)
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{
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const struct spi_litex_cfg *dev_config = dev->config;
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if (!dev_config->clk_divider_exists) {
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/* The clk_divider is optional, thats why we check. */
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LOG_WRN("No clk_divider found, can't change frequency");
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return;
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}
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uint16_t divisor = DIV_ROUND_UP(sys_clock_hw_cycles_per_sec(), config->frequency);
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litex_write16(divisor, dev_config->clk_divider_addr);
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}
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/* Helper Functions */
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static int spi_config(const struct device *dev, const struct spi_config *config, uint16_t *control)
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{
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const struct spi_litex_cfg *dev_config = dev->config;
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struct spi_litex_data *dev_data = dev->data;
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if (config->slave >= dev_config->max_cs) {
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LOG_ERR("More slaves than supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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if (SPI_WORD_SIZE_GET(config->operation) > dev_config->data_width) {
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LOG_ERR("Word size must be <= %d", dev_config->data_width);
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return -ENOTSUP;
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}
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if (config->operation & SPI_CS_ACTIVE_HIGH) {
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LOG_ERR("CS active high not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_LOCK_ON) {
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LOG_ERR("Lock On not supported");
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return -ENOTSUP;
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}
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if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
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(config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only supports single mode");
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return -ENOTSUP;
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("LSB first not supported");
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return -ENOTSUP;
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}
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if (config->operation & (SPI_MODE_CPOL | SPI_MODE_CPHA)) {
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LOG_ERR("Only supports CPOL=CPHA=0");
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return -ENOTSUP;
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}
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if (config->operation & SPI_OP_MODE_SLAVE) {
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LOG_ERR("Slave mode not supported");
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return -ENOTSUP;
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}
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/* Set Loopback */
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if (!litex_read8(dev_config->loopback_addr) != !(config->operation & SPI_MODE_LOOP)) {
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litex_write8(((config->operation & SPI_MODE_LOOP) ? 0x1 : 0x0),
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dev_config->loopback_addr);
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}
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/* Set word size */
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*control = (uint16_t) (SPI_WORD_SIZE_GET(config->operation)
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<< POSITION_WORD_SIZE);
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dev_data->dfs = get_dfs_value(config);
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/* Write configurations */
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litex_write16(*control, dev_config->control_addr);
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spi_set_frequency(dev, config);
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return 0;
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}
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static void spi_litex_send(const struct device *dev, uint32_t frame,
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uint16_t control)
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{
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const struct spi_litex_cfg *dev_config = dev->config;
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/* Write frame to register */
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litex_write32(frame, dev_config->mosi_addr);
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/* Start the transfer */
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litex_write16(control | BIT(0), dev_config->control_addr);
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/* Wait until the transfer ends */
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while (!(litex_read8(dev_config->status_addr) & BIT(0))) {
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;/* Wait */
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}
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}
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static uint32_t spi_litex_recv(const struct device *dev)
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{
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const struct spi_litex_cfg *dev_config = dev->config;
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/* Return data inside MISO register */
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return litex_read32(dev_config->miso_addr);
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}
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static void spi_litex_xfer(const struct device *dev,
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const struct spi_config *config,
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uint16_t control)
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{
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const struct spi_litex_cfg *dev_config = dev->config;
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struct spi_litex_data *dev_data = dev->data;
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struct spi_context *ctx = &dev_data->ctx;
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uint32_t txd, rxd;
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/* Set CS */
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litex_write16(BIT(config->slave), dev_config->cs_addr);
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do {
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/* Send a frame */
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if (spi_context_tx_buf_on(ctx)) {
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litex_spi_tx_put(dev_data->dfs, &txd, ctx->tx_buf);
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} else {
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txd = 0U;
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}
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LOG_DBG("txd: 0x%x", txd);
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spi_litex_send(dev, txd, control);
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spi_context_update_tx(ctx, dev_data->dfs, 1);
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rxd = spi_litex_recv(dev);
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LOG_DBG("rxd: 0x%x", rxd);
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if (spi_context_rx_buf_on(ctx)) {
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litex_spi_rx_put(dev_data->dfs, &rxd, ctx->rx_buf);
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}
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spi_context_update_rx(ctx, dev_data->dfs, 1);
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} while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx));
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spi_context_complete(ctx, dev, 0);
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/* Clear CS */
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litex_write16(0, dev_config->cs_addr);
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}
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/* API Functions */
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static int spi_litex_transceive(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct spi_litex_data *dev_data = dev->data;
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uint16_t control = 0;
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int ret = 0;
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ret = spi_config(dev, config, &control);
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if (ret < 0) {
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return ret;
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}
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spi_context_buffers_setup(&dev_data->ctx, tx_bufs, rx_bufs, dev_data->dfs);
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spi_litex_xfer(dev, config, control);
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return 0;
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_litex_transceive_async(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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struct k_poll_signal *async)
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{
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return -ENOTSUP;
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}
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#endif /* CONFIG_SPI_ASYNC */
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static int spi_litex_release(const struct device *dev, const struct spi_config *config)
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{
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const struct spi_litex_cfg *dev_config = dev->config;
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if (!(litex_read8(dev_config->status_addr) & BIT(0))) {
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return -EBUSY;
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}
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return 0;
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}
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/* Device Instantiation */
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static const struct spi_driver_api spi_litex_api = {
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.transceive = spi_litex_transceive,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_litex_transceive_async,
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#endif /* CONFIG_SPI_ASYNC */
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#ifdef CONFIG_SPI_RTIO
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.iodev_submit = spi_rtio_iodev_default_submit,
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#endif
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.release = spi_litex_release,
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};
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#define SPI_INIT(n) \
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static struct spi_litex_data spi_litex_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_litex_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_litex_data_##n, ctx), \
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}; \
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static struct spi_litex_cfg spi_litex_cfg_##n = { \
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.control_addr = DT_INST_REG_ADDR_BY_NAME(n, control), \
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.status_addr = DT_INST_REG_ADDR_BY_NAME(n, status), \
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.mosi_addr = DT_INST_REG_ADDR_BY_NAME(n, mosi), \
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.miso_addr = DT_INST_REG_ADDR_BY_NAME(n, miso), \
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.cs_addr = DT_INST_REG_ADDR_BY_NAME(n, cs), \
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.loopback_addr = DT_INST_REG_ADDR_BY_NAME(n, loopback), \
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.clk_divider_exists = DT_INST_REG_HAS_NAME(n, clk_divider), \
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.clk_divider_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, clk_divider, 0), \
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.data_width = DT_INST_PROP(n, data_width), \
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.max_cs = DT_INST_PROP(n, max_cs), \
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}; \
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DEVICE_DT_INST_DEFINE(n, \
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NULL, \
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NULL, \
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&spi_litex_data_##n, \
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&spi_litex_cfg_##n, \
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POST_KERNEL, \
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CONFIG_SPI_INIT_PRIORITY, \
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&spi_litex_api);
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DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)
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