431 lines
13 KiB
C
431 lines
13 KiB
C
/*
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* Copyright (c) 2024 Ambiq <www.ambiq.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ambiq_spid
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_ambiq_spid);
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/policy.h>
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#include <zephyr/pm/device_runtime.h>
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#include <stdlib.h>
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#include <errno.h>
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#include "spi_context.h"
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#include <am_mcu_apollo.h>
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#define AMBIQ_SPID_PWRCTRL_MAX_WAIT_US 5
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typedef int (*ambiq_spi_pwr_func_t)(void);
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struct spi_ambiq_config {
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const struct gpio_dt_spec int_gpios;
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uint32_t base;
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int size;
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const struct pinctrl_dev_config *pcfg;
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ambiq_spi_pwr_func_t pwr_func;
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void (*irq_config_func)(void);
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};
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struct spi_ambiq_data {
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struct spi_context ctx;
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am_hal_ios_config_t ios_cfg;
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void *ios_handler;
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int inst_idx;
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struct k_sem spim_wrcmp_sem;
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};
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#define AMBIQ_SPID_TX_BUFSIZE_MAX 1023
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uint8_t ambiq_spid_sram_buffer[AMBIQ_SPID_TX_BUFSIZE_MAX];
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#define AMBIQ_SPID_DUMMY_BYTE 0
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#define AMBIQ_SPID_DUMMY_LENGTH 16
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static uint8_t ambiq_spid_dummy_buffer[2][AMBIQ_SPID_DUMMY_LENGTH];
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#define AMBIQ_SPID_WORD_SIZE 8
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#define AMBIQ_SPID_FIFO_BASE 0x78
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#define AMBIQ_SPID_FIFO_END 0x100
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#define AMBIQ_SPID_FIFO_LENGTH (AMBIQ_SPID_FIFO_END - AMBIQ_SPID_FIFO_BASE)
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#define AMBIQ_SPID_INT_ERR (AM_HAL_IOS_INT_FOVFL | AM_HAL_IOS_INT_FUNDFL | AM_HAL_IOS_INT_FRDERR)
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#define AMBIQ_SPID_XCMP_INT \
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(AM_HAL_IOS_INT_XCMPWR | AM_HAL_IOS_INT_XCMPWF | AM_HAL_IOS_INT_XCMPRR | \
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AM_HAL_IOS_INT_XCMPRF)
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static void spi_ambiq_reset(const struct device *dev)
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{
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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/* cancel timed out transaction */
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am_hal_ios_disable(data->ios_handler);
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/* NULL config to trigger reconfigure on next xfer */
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ctx->config = NULL;
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/* signal any thread waiting on sync semaphore */
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spi_context_complete(ctx, dev, -ETIMEDOUT);
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}
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static void spi_ambiq_inform(const struct device *dev)
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{
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const struct spi_ambiq_config *cfg = dev->config;
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/* Inform the controller */
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gpio_pin_set_dt(&cfg->int_gpios, 1);
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gpio_pin_set_dt(&cfg->int_gpios, 0);
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}
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static void spi_ambiq_isr(const struct device *dev)
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{
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uint32_t ui32Status;
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struct spi_ambiq_data *data = dev->data;
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am_hal_ios_interrupt_status_get(data->ios_handler, false, &ui32Status);
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am_hal_ios_interrupt_clear(data->ios_handler, ui32Status);
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if (ui32Status & AM_HAL_IOS_INT_XCMPWR) {
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k_sem_give(&data->spim_wrcmp_sem);
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}
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}
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static int spi_config(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &(data->ctx);
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int ret = 0;
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data->ios_cfg.ui32InterfaceSelect = AM_HAL_IOS_USE_SPI;
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if (spi_context_configured(ctx, config)) {
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/* Already configured. No need to do it again. */
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return 0;
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}
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if (SPI_WORD_SIZE_GET(config->operation) != AMBIQ_SPID_WORD_SIZE) {
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LOG_ERR("Word size must be %d", AMBIQ_SPID_WORD_SIZE);
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return -ENOTSUP;
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}
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if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only supports single mode");
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return -ENOTSUP;
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}
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if (config->operation & SPI_LOCK_ON) {
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LOG_ERR("Lock On not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("LSB first not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_MODE_CPOL) {
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if (config->operation & SPI_MODE_CPHA) {
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data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_3;
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} else {
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data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_2;
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}
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} else {
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if (config->operation & SPI_MODE_CPHA) {
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data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_1;
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} else {
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data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_0;
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}
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}
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if (config->operation & SPI_OP_MODE_MASTER) {
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LOG_ERR("Controller mode not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_MODE_LOOP) {
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LOG_ERR("Loopback mode not supported");
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return -ENOTSUP;
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}
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if (spi_cs_is_gpio(config)) {
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LOG_ERR("CS control via GPIO is not supported");
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return -EINVAL;
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}
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/* Eliminate the "read-only" section, so an external controller can use the
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* entire "direct write" section.
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*/
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data->ios_cfg.ui32ROBase = AMBIQ_SPID_FIFO_BASE;
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/* Making the "FIFO" section as big as possible. */
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data->ios_cfg.ui32FIFOBase = AMBIQ_SPID_FIFO_BASE;
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/* We don't need any RAM space, so extend the FIFO all the way to the end
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* of the LRAM.
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*/
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data->ios_cfg.ui32RAMBase = AMBIQ_SPID_FIFO_END;
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/* FIFO Threshold - set to half the size */
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data->ios_cfg.ui32FIFOThreshold = AMBIQ_SPID_FIFO_LENGTH >> 1;
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data->ios_cfg.pui8SRAMBuffer = ambiq_spid_sram_buffer,
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data->ios_cfg.ui32SRAMBufferCap = AMBIQ_SPID_TX_BUFSIZE_MAX,
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ctx->config = config;
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ret = am_hal_ios_configure(data->ios_handler, &data->ios_cfg);
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return ret;
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}
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static int spi_ambiq_xfer(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int ret = 0;
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uint32_t chunk, num_written, num_read, used_space = 0;
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while (1) {
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/* First send out all data */
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if (spi_context_tx_on(ctx)) {
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spi_ambiq_inform(dev);
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chunk = (ctx->tx_len > AMBIQ_SPID_TX_BUFSIZE_MAX)
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? AMBIQ_SPID_TX_BUFSIZE_MAX
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: ctx->tx_len;
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am_hal_ios_fifo_space_used(data->ios_handler, &used_space);
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/* Controller done reading the last block signalled
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* Check if any more data available
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*/
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if (!used_space) {
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if (ctx->tx_buf) {
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/* Copy data into FIFO */
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ret = am_hal_ios_fifo_write(data->ios_handler,
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(uint8_t *)ctx->tx_buf, chunk,
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&num_written);
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} else {
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uint32_t dummy_written = 0;
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num_written = 0;
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/* Copy dummy into FIFO */
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while (chunk) {
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uint32_t size = (chunk > AMBIQ_SPID_DUMMY_LENGTH)
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? AMBIQ_SPID_DUMMY_LENGTH
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: chunk;
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ret = am_hal_ios_fifo_write(
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data->ios_handler,
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ambiq_spid_dummy_buffer[0], size,
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&dummy_written);
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num_written += dummy_written;
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chunk -= dummy_written;
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}
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}
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if (ret != 0) {
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LOG_ERR("SPID write error: %d", ret);
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goto end;
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}
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spi_context_update_tx(ctx, 1, num_written);
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}
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} else if (spi_context_rx_on(ctx)) {
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/* Wait for controller write complete interrupt */
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(void)k_sem_take(&data->spim_wrcmp_sem, K_FOREVER);
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/* Read out the first byte as packet length */
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num_read = am_hal_ios_pui8LRAM[0];
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uint32_t size, offset = 0;
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while (spi_context_rx_on(ctx)) {
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/* There's no data in the LRAM any more */
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if (!num_read) {
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spi_ambiq_inform(dev);
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goto end;
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}
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if (ctx->rx_buf) {
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size = MIN(num_read, ctx->rx_len);
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/* Read data from LRAM */
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memcpy(ctx->rx_buf,
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(uint8_t *)&am_hal_ios_pui8LRAM[1 + offset], size);
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} else {
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size = MIN(num_read, AMBIQ_SPID_DUMMY_LENGTH);
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/* Consume data from LRAM */
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memcpy(ambiq_spid_dummy_buffer[1],
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(uint8_t *)&am_hal_ios_pui8LRAM[1 + offset], size);
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}
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num_read -= size;
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offset += size;
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spi_context_update_rx(ctx, 1, size);
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}
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} else {
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break;
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}
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}
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end:
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if (ret != 0) {
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spi_ambiq_reset(dev);
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} else {
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spi_context_complete(ctx, dev, ret);
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}
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return ret;
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}
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static int spi_ambiq_transceive(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct spi_ambiq_data *data = dev->data;
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int ret;
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if (!tx_bufs && !rx_bufs) {
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return 0;
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}
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ret = pm_device_runtime_get(dev);
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if (ret < 0) {
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LOG_ERR("pm_device_runtime_get failed: %d", ret);
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}
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/* context setup */
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spi_context_lock(&data->ctx, false, NULL, NULL, config);
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ret = spi_config(dev, config);
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if (ret) {
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spi_context_release(&data->ctx, ret);
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return ret;
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}
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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ret = spi_ambiq_xfer(dev, config);
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spi_context_release(&data->ctx, ret);
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/* Use async put to avoid useless device suspension/resumption
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* when doing consecutive transmission.
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*/
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ret = pm_device_runtime_put_async(dev, K_MSEC(2));
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if (ret < 0) {
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LOG_ERR("pm_device_runtime_put failed: %d", ret);
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}
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return ret;
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}
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static int spi_ambiq_release(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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if (!spi_context_configured(&data->ctx, config)) {
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return -EINVAL;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct spi_driver_api spi_ambiq_driver_api = {
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.transceive = spi_ambiq_transceive,
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.release = spi_ambiq_release,
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};
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static int spi_ambiq_init(const struct device *dev)
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{
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struct spi_ambiq_data *data = dev->data;
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const struct spi_ambiq_config *cfg = dev->config;
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int ret = 0;
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if (AM_HAL_STATUS_SUCCESS !=
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am_hal_ios_initialize((cfg->base - IOSLAVE_BASE) / cfg->size, &data->ios_handler)) {
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LOG_ERR("Fail to initialize SPID\n");
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return -ENXIO;
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}
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ret = cfg->pwr_func();
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ret |= pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("Fail to config SPID pins\n");
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goto end;
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}
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memset(ambiq_spid_dummy_buffer[0], AMBIQ_SPID_DUMMY_BYTE, AMBIQ_SPID_DUMMY_LENGTH);
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am_hal_ios_interrupt_clear(data->ios_handler, AM_HAL_IOS_INT_ALL);
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am_hal_ios_interrupt_enable(data->ios_handler, AMBIQ_SPID_INT_ERR | AM_HAL_IOS_INT_IOINTW |
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AMBIQ_SPID_XCMP_INT);
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cfg->irq_config_func();
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end:
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if (ret < 0) {
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am_hal_ios_uninitialize(data->ios_handler);
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} else {
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spi_context_unlock_unconditionally(&data->ctx);
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}
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return ret;
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}
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#ifdef CONFIG_PM_DEVICE
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static int spi_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
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{
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struct spi_ambiq_data *data = dev->data;
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uint32_t ret;
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am_hal_sysctrl_power_state_e status;
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switch (action) {
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case PM_DEVICE_ACTION_RESUME:
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status = AM_HAL_SYSCTRL_WAKE;
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break;
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case PM_DEVICE_ACTION_SUSPEND:
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status = AM_HAL_SYSCTRL_DEEPSLEEP;
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break;
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default:
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return -ENOTSUP;
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}
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ret = am_hal_ios_power_ctrl(data->ios_handler, status, true);
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if (ret != AM_HAL_STATUS_SUCCESS) {
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LOG_ERR("am_hal_ios_power_ctrl failed: %d", ret);
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return -EPERM;
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} else {
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return 0;
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}
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}
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#endif /* CONFIG_PM_DEVICE */
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#define AMBIQ_SPID_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static int pwr_on_ambiq_spi_##n(void) \
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{ \
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uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
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DT_INST_PHA(n, ambiq_pwrcfg, offset); \
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sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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k_busy_wait(AMBIQ_SPID_PWRCTRL_MAX_WAIT_US); \
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return 0; \
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} \
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static void spi_irq_config_func_##n(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_ambiq_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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}; \
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static struct spi_ambiq_data spi_ambiq_data##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_ambiq_data##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_ambiq_data##n, ctx), \
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.spim_wrcmp_sem = Z_SEM_INITIALIZER(spi_ambiq_data##n.spim_wrcmp_sem, 0, 1), \
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.inst_idx = n}; \
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static const struct spi_ambiq_config spi_ambiq_config##n = { \
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.int_gpios = GPIO_DT_SPEC_INST_GET(n, int_gpios), \
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.base = DT_INST_REG_ADDR(n), \
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.size = DT_INST_REG_SIZE(n), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.irq_config_func = spi_irq_config_func_##n, \
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.pwr_func = pwr_on_ambiq_spi_##n}; \
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PM_DEVICE_DT_INST_DEFINE(n, spi_ambiq_pm_action); \
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DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, PM_DEVICE_DT_INST_GET(n), &spi_ambiq_data##n, \
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&spi_ambiq_config##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
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&spi_ambiq_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(AMBIQ_SPID_INIT)
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