117 lines
3.3 KiB
C
117 lines
3.3 KiB
C
/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/gd32.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <gd32_gpio.h>
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BUILD_ASSERT((GD32_PUPD_NONE == GPIO_PUPD_NONE) &&
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(GD32_PUPD_PULLUP == GPIO_PUPD_PULLUP) &&
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(GD32_PUPD_PULLDOWN == GPIO_PUPD_PULLDOWN),
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"pinctrl pull-up/down definitions != HAL definitions");
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BUILD_ASSERT((GD32_OTYPE_PP == GPIO_OTYPE_PP) &&
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(GD32_OTYPE_OD == GPIO_OTYPE_OD),
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"pinctrl output type definitions != HAL definitions");
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BUILD_ASSERT((GD32_OSPEED_2MHZ == GPIO_OSPEED_2MHZ) &&
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#if defined(CONFIG_SOC_SERIES_GD32F3X0) || \
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defined(CONFIG_SOC_SERIES_GD32A50X) || \
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defined(CONFIG_SOC_SERIES_GD32L23X)
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(GD32_OSPEED_10MHZ == GPIO_OSPEED_10MHZ) &&
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(GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) &&
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#else
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(GD32_OSPEED_25MHZ == GPIO_OSPEED_25MHZ) &&
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(GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) &&
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(GD32_OSPEED_MAX == GPIO_OSPEED_MAX) &&
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#endif
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1U,
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"pinctrl output speed definitions != HAL definitions");
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/** Utility macro that expands to the GPIO port address if it exists */
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#define GD32_PORT_ADDR_OR_NONE(nodelabel) \
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COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
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(DT_REG_ADDR(DT_NODELABEL(nodelabel)),), ())
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/** Utility macro that expands to the GPIO clock id if it exists */
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#define GD32_PORT_CLOCK_ID_OR_NONE(nodelabel) \
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COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
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(DT_CLOCKS_CELL(DT_NODELABEL(nodelabel), id),), ())
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/** GD32 port addresses */
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static const uint32_t gd32_port_addrs[] = {
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GD32_PORT_ADDR_OR_NONE(gpioa)
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GD32_PORT_ADDR_OR_NONE(gpiob)
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GD32_PORT_ADDR_OR_NONE(gpioc)
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GD32_PORT_ADDR_OR_NONE(gpiod)
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GD32_PORT_ADDR_OR_NONE(gpioe)
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GD32_PORT_ADDR_OR_NONE(gpiof)
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GD32_PORT_ADDR_OR_NONE(gpiog)
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GD32_PORT_ADDR_OR_NONE(gpioh)
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GD32_PORT_ADDR_OR_NONE(gpioi)
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};
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/** GD32 port clock identifiers */
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static const uint16_t gd32_port_clkids[] = {
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GD32_PORT_CLOCK_ID_OR_NONE(gpioa)
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GD32_PORT_CLOCK_ID_OR_NONE(gpiob)
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GD32_PORT_CLOCK_ID_OR_NONE(gpioc)
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GD32_PORT_CLOCK_ID_OR_NONE(gpiod)
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GD32_PORT_CLOCK_ID_OR_NONE(gpioe)
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GD32_PORT_CLOCK_ID_OR_NONE(gpiof)
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GD32_PORT_CLOCK_ID_OR_NONE(gpiog)
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GD32_PORT_CLOCK_ID_OR_NONE(gpioh)
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GD32_PORT_CLOCK_ID_OR_NONE(gpioi)
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};
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/**
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* @brief Configure a pin.
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*
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* @param pin The pin to configure.
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*/
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static void pinctrl_configure_pin(pinctrl_soc_pin_t pin)
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{
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uint8_t port_idx;
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uint32_t port, pin_num, af, mode;
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uint16_t clkid;
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port_idx = GD32_PORT_GET(pin);
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__ASSERT_NO_MSG(port_idx < ARRAY_SIZE(gd32_port_addrs));
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clkid = gd32_port_clkids[port_idx];
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port = gd32_port_addrs[port_idx];
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pin_num = BIT(GD32_PIN_GET(pin));
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af = GD32_AF_GET(pin);
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(void)clock_control_on(GD32_CLOCK_CONTROLLER,
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(clock_control_subsys_t)&clkid);
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if (af != GD32_ANALOG) {
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mode = GPIO_MODE_AF;
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gpio_af_set(port, af, pin_num);
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} else {
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mode = GPIO_MODE_ANALOG;
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}
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gpio_mode_set(port, mode, GD32_PUPD_GET(pin), pin_num);
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gpio_output_options_set(port, GD32_OTYPE_GET(pin),
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GD32_OSPEED_GET(pin), pin_num);
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_configure_pin(pins[i]);
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}
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return 0;
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}
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