99 lines
2.5 KiB
C
99 lines
2.5 KiB
C
/*
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* Copyright (c) 2018 - 2021 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT litex_vexriscv_intc0
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/irq.h>
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#include <zephyr/device.h>
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#include <zephyr/types.h>
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#include <zephyr/arch/riscv/irq.h>
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#define IRQ_MASK DT_INST_REG_ADDR_BY_NAME(0, irq_mask)
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#define IRQ_PENDING DT_INST_REG_ADDR_BY_NAME(0, irq_pending)
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static inline void vexriscv_litex_irq_setmask(uint32_t mask)
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{
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__asm__ volatile ("csrw %0, %1" :: "i"(IRQ_MASK), "r"(mask));
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}
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static inline uint32_t vexriscv_litex_irq_getmask(void)
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{
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uint32_t mask;
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__asm__ volatile ("csrr %0, %1" : "=r"(mask) : "i"(IRQ_MASK));
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return mask;
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}
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static inline uint32_t vexriscv_litex_irq_pending(void)
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{
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uint32_t pending;
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__asm__ volatile ("csrr %0, %1" : "=r"(pending) : "i"(IRQ_PENDING));
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return pending;
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}
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static inline void vexriscv_litex_irq_setie(uint32_t ie)
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{
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if (ie) {
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__asm__ volatile ("csrrs x0, mstatus, %0"
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:: "r"(MSTATUS_IEN));
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} else {
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__asm__ volatile ("csrrc x0, mstatus, %0"
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:: "r"(MSTATUS_IEN));
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}
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}
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#define LITEX_IRQ_ADD_HELPER(n) \
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if (irqs & (1 << DT_IRQN(n))) { \
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ite = &_sw_isr_table[DT_IRQN(n)]; \
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ite->isr(ite->arg); \
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}
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#define LITEX_IRQ_ADD(n) IF_ENABLED(DT_IRQ_HAS_IDX(n, 0), (LITEX_IRQ_ADD_HELPER(n)))
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static void vexriscv_litex_irq_handler(const void *device)
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{
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struct _isr_table_entry *ite;
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uint32_t pending, mask, irqs;
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pending = vexriscv_litex_irq_pending();
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mask = vexriscv_litex_irq_getmask();
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irqs = pending & mask;
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DT_FOREACH_STATUS_OKAY_NODE(LITEX_IRQ_ADD);
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}
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void arch_irq_enable(unsigned int irq)
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{
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vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() | (1 << irq));
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}
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void arch_irq_disable(unsigned int irq)
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{
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vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() & ~(1 << irq));
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}
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int arch_irq_is_enabled(unsigned int irq)
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{
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return vexriscv_litex_irq_getmask() & (1 << irq);
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}
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static int vexriscv_litex_irq_init(const struct device *dev)
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{
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__asm__ volatile ("csrrs x0, mie, %0"
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:: "r"(1 << RISCV_IRQ_MEXT));
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vexriscv_litex_irq_setie(1);
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IRQ_CONNECT(RISCV_IRQ_MEXT, 0, vexriscv_litex_irq_handler,
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NULL, 0);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, vexriscv_litex_irq_init, NULL, NULL, NULL,
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PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
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