174 lines
4.0 KiB
C
174 lines
4.0 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef DMA_PL330_H
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#define DMA_PL330_H
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#include <zephyr/drivers/dma.h>
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#define DT_DRV_COMPAT arm_dma_pl330
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/*
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* Max burst length and max burst size for 32bit system with
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* 128bit bus width for memory to memory data transfer
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*
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* Burst length is encoded in following format for pl330
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* b0000 = 1 data transfer
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* b0001 = 2 data transfers
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* b0010 = 3 data transfers
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* .
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* .
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* b1111 = 16 data transfers
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*
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* Burst size is encoded in following format for pl330
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* b000 = 1 byte
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* b001 = 2 bytes
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* b010 = 4 bytes
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* b011 = 8 bytes
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* b100 = 16 bytes
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* b101 = 32 bytes
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* b110 = 64 bytes
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* b111 = 128 bytes.
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*/
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#define MAX_BURST_LEN 0xf /* 16byte data */
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#define MAX_BURST_SIZE_LOG2 4
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/*
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* PL330 works only on 4GB boundary.
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* PL330 has 32bit registers for source and destination addresses
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*/
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#define PL330_MAX_OFFSET 0x100000000
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/* PL330 supports max 16MB dma based on AXI bus size */
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#define PL330_MAX_DMA_SIZE 0x1000000
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/* Maximum possible values for PL330 ucode loop counters */
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#define PL330_LOOP_COUNTER0_MAX 0x100
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#define PL330_LOOP_COUNTER1_MAX 0x100
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#define MAX_DMA_CHANNELS DT_INST_PROP(0, dma_channels)
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#define DMAC_PL330_CS0 0x100
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#define DMAC_PL330_DBGSTATUS 0xd00
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#define DMAC_PL330_DBGCMD 0xd04
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#define DMAC_PL330_DBGINST0 0xd08
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#define DMAC_PL330_DBGINST1 0xd0c
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/*
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* TIMEOUT value of 100000us is kept to cover all possible data
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* transfer sizes, with lesser time out value(10us) DMA channel
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* appears to be busy on FPGA/Emul environment. Ideally 100000us
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* timeout value should never hit.
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*/
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#define DMA_TIMEOUT_US 100000
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#define CH_STATUS_MASK 0xf
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#define DATA_MASK 0xf
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#define DMA_INTSR1_SHIFT 24
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#define DMA_INTSR0_SHIFT 16
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#define DMA_INTSR0 0xa0
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#define DMA_SECURE_SHIFT 17
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#define DMA_CH_SHIFT 8
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#define CONTROL_OFFSET 0x4
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#define HIGHER_32_ADDR_MASK 0x0f
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#define DST_ADDR_SHIFT 0x4
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#define MICROCODE_SIZE_MAX 0x400
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#define TOTAL_MICROCODE_SIZE (MAX_DMA_CHANNELS * MICROCODE_SIZE_MAX)
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#define GET_MAX_DMA_SIZE(byte_width, burst_len) \
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(PL330_LOOP_COUNTER0_MAX * PL330_LOOP_COUNTER1_MAX * \
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(byte_width) * ((burst_len) + 1))
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#define CC_SRCINC_SHIFT 0
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#define CC_DSTINC_SHIFT 14
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#define CC_SRCPRI_SHIFT 8
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#define CC_DSTPRI_SHIFT 22
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#define CC_DSTNS_SHIFT 23
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#define CC_SRCBRSTLEN_SHIFT 4
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#define CC_DSTBRSTLEN_SHIFT 18
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#define CC_SRCBRSTSIZE_SHIFT 1
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#define CC_DSTBRSTSIZE_SHIFT 15
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#define CC_SRCCCTRL_SHIFT 11
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#define CC_SRCCCTRL_MASK 0x7
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#define CC_DSTCCTRL_SHIFT 25
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#define CC_DRCCCTRL_MASK 0x7
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#define CC_SWAP_SHIFT 28
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#define SRC_PRI_NONSEC_VALUE 0x2
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#define SRC_PRI_SEC_VALUE 0x0
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#define OP_DMA_MOV 0xbc
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#define OP_DMA_LOOP_COUNT1 0x22
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#define OP_DMA_LOOP 0x20
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#define OP_DMA_LD 0x4
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#define OP_DMA_ST 0x8
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#define OP_DMA_SEV 0x34
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#define OP_DMA_END 0x00
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#define OP_DMA_LP_BK_JMP1 0x38
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#define OP_DMA_LP_BK_JMP2 0x3c
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#define SZ_CMD_DMAMOV 0x6
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enum dmamov_type {
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/* Source Address Register */
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SAR = 0,
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/* Channel Control Register */
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CCR,
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/* Destination Address Register */
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DAR,
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};
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/* Channel specific private data */
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struct dma_pl330_ch_internal {
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uint64_t src_addr;
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uint64_t dst_addr;
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int src_burst_sz;
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uint32_t src_burst_len;
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int dst_burst_sz;
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uint32_t dst_burst_len;
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uint32_t trans_size;
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uint32_t dst_id;
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uint32_t src_id;
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uint32_t perip_type;
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uint32_t breq_only;
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uint32_t src_cache_ctrl;
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uint32_t dst_cache_ctrl;
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uint32_t dst_inc;
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uint32_t src_inc;
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int nonsec_mode;
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};
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struct dma_pl330_ch_config {
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/* Channel configuration details */
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uint64_t src_addr;
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enum dma_addr_adj src_addr_adj;
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uint64_t dst_addr;
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enum dma_addr_adj dst_addr_adj;
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enum dma_channel_direction direction;
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uint32_t trans_size;
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void *user_data;
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dma_callback_t dma_callback;
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mem_addr_t dma_exec_addr;
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struct k_mutex ch_mutex;
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int channel_active;
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/* Channel specific private data */
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struct dma_pl330_ch_internal internal;
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};
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struct dma_pl330_config {
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mem_addr_t mcode_base;
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mem_addr_t reg_base;
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#ifdef CONFIG_DMA_64BIT
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mem_addr_t control_reg_base;
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#endif
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};
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struct dma_pl330_dev_data {
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struct dma_pl330_ch_config channels[MAX_DMA_CHANNELS];
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};
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#endif
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