54 lines
1.2 KiB
Plaintext
54 lines
1.2 KiB
Plaintext
# DesignWare DMA configuration options
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# Copyright (c) 2023 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config DMA_DW_AXI
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bool "DesignWare AXI DMA driver"
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default y
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depends on DT_HAS_SNPS_DESIGNWARE_DMA_AXI_ENABLED
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imply DMA_64BIT
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help
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DesignWare AXI DMA driver.
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if DMA_DW_AXI
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config DMA_DW_AXI_MAX_DESC
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int "allocate number of lli descriptor"
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default 10
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help
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creates number of descriptor per channel in a statically allocated pool.
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Each channel has its own dedicated pool.
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config DMA_DW_AXI_LLI_SUPPORT
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bool "hardware supports linked list multi block transfer"
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default y
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help
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This flag can be enabled if hardware support Linked List multi-block transfer
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config DMA_CHANNEL_STATUS_TIMEOUT
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int "Channel status timeout"
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default 1000
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help
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Max timeout to abort or disable the channel
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config DMA_DW_AXI_MAX_BURST_TXN_LEN
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int "max burst transaction length"
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default 8
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help
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set max number of source and destination data units supported
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config DMA_DW_AXI_DATA_WIDTH
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int "data bus width"
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default 64
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help
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update this flag to change the axi master interface data width
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config DMA_DW_AXI_MAX_BLOCK_TS
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int "max block size"
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default 32767
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help
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update this config to set maximum value of block size
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endif # DMA_DW_AXI
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