269 lines
7.8 KiB
C
269 lines
7.8 KiB
C
/*
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* Copyright (c) 2020 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_pcc
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#include <soc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/npcx_clock.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(clock_control_npcx, LOG_LEVEL_ERR);
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/* Driver config */
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struct npcx_pcc_config {
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/* cdcg device base address */
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uintptr_t base_cdcg;
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/* pmc device base address */
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uintptr_t base_pmc;
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};
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/* Driver convenience defines */
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#define HAL_CDCG_INST(dev) \
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((struct cdcg_reg *)((const struct npcx_pcc_config *)(dev)->config)->base_cdcg)
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#define HAL_PMC_INST(dev) \
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((struct pmc_reg *)((const struct npcx_pcc_config *)(dev)->config)->base_pmc)
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static uint8_t pddwn_ctl_val[] = {NPCX_PWDWN_CTL_INIT};
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/* Clock controller local functions */
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static inline int npcx_clock_control_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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ARG_UNUSED(dev);
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struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
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const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;
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if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) {
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return -EINVAL;
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}
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/* Clear related PD (Power-Down) bit of module to turn on clock */
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NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) &= ~(BIT(clk_cfg->bit));
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return 0;
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}
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static inline int npcx_clock_control_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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ARG_UNUSED(dev);
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struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
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const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;
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if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) {
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return -EINVAL;
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}
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/* Set related PD (Power-Down) bit of module to turn off clock */
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NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) |= BIT(clk_cfg->bit);
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return 0;
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}
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static int npcx_clock_control_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(dev);
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struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
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switch (clk_cfg->bus) {
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case NPCX_CLOCK_BUS_APB1:
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*rate = NPCX_APB_CLOCK(1);
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break;
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case NPCX_CLOCK_BUS_APB2:
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*rate = NPCX_APB_CLOCK(2);
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break;
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case NPCX_CLOCK_BUS_APB3:
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*rate = NPCX_APB_CLOCK(3);
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break;
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#if defined(APB4DIV_VAL)
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case NPCX_CLOCK_BUS_APB4:
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*rate = NPCX_APB_CLOCK(4);
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break;
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#endif
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case NPCX_CLOCK_BUS_AHB6:
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*rate = CORE_CLK/(AHB6DIV_VAL + 1);
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break;
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case NPCX_CLOCK_BUS_FIU:
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*rate = CORE_CLK/(FIUDIV_VAL + 1);
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break;
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#if defined(FIU1DIV_VAL)
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case NPCX_CLOCK_BUS_FIU1:
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*rate = CORE_CLK/(FIU1DIV_VAL + 1);
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break;
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#endif
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case NPCX_CLOCK_BUS_CORE:
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*rate = CORE_CLK;
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break;
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case NPCX_CLOCK_BUS_LFCLK:
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*rate = LFCLK;
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break;
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case NPCX_CLOCK_BUS_FMCLK:
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*rate = FMCLK;
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break;
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case NPCX_CLOCK_BUS_MCLKD:
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*rate = OFMCLK/(MCLKD_SL + 1);
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break;
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default:
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*rate = 0U;
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/* Invalid parameters */
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return -EINVAL;
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}
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return 0;
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}
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/* Platform specific clock controller functions */
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#if defined(CONFIG_PM)
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void npcx_clock_control_turn_on_system_sleep(bool is_deep, bool is_instant)
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{
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const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
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struct pmc_reg *const inst_pmc = HAL_PMC_INST(clk_dev);
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/* Configure that ec enters system sleep mode if receiving 'wfi' */
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uint8_t pm_flags = BIT(NPCX_PMCSR_IDLE);
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/* Add 'Disable High-Frequency' flag (ie. 'deep sleep' mode) */
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if (is_deep) {
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pm_flags |= BIT(NPCX_PMCSR_DHF);
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/* Add 'Instant Wake-up' flag if sleep time is within 200 ms */
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if (is_instant) {
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pm_flags |= BIT(NPCX_PMCSR_DI_INSTW);
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}
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}
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inst_pmc->PMCSR = pm_flags;
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}
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void npcx_clock_control_turn_off_system_sleep(void)
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{
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const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
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struct pmc_reg *const inst_pmc = HAL_PMC_INST(clk_dev);
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inst_pmc->PMCSR = 0;
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}
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#endif /* CONFIG_PM */
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/* Clock controller driver registration */
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static const struct clock_control_driver_api npcx_clock_control_api = {
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.on = npcx_clock_control_on,
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.off = npcx_clock_control_off,
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.get_rate = npcx_clock_control_get_subsys_rate,
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};
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/* valid clock frequency check */
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BUILD_ASSERT(OFMCLK <= MAX_OFMCLK, "Exceed maximum OFMCLK setting");
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BUILD_ASSERT(CORE_CLK <= MAX_OFMCLK && CORE_CLK >= MHZ(4) &&
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OFMCLK % CORE_CLK == 0 &&
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OFMCLK / CORE_CLK <= 10,
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"Invalid CORE_CLK setting");
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BUILD_ASSERT(CORE_CLK / (FIUDIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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CORE_CLK / (FIUDIV_VAL + 1) >= MHZ(4),
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"Invalid FIUCLK setting");
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#if defined(FIU1DIV_VAL)
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BUILD_ASSERT(CORE_CLK / (FIU1DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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CORE_CLK / (FIU1DIV_VAL + 1) >= MHZ(4),
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"Invalid FIU1CLK setting");
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#endif
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BUILD_ASSERT(CORE_CLK / (AHB6DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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CORE_CLK / (AHB6DIV_VAL + 1) >= MHZ(4),
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"Invalid AHB6_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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APBSRC_CLK / (APB1DIV_VAL + 1) >= MHZ(4) &&
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(APB1DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB1_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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APBSRC_CLK / (APB2DIV_VAL + 1) >= MHZ(8) &&
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(APB2DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB2_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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APBSRC_CLK / (APB3DIV_VAL + 1) >= KHZ(12500) &&
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(APB3DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB3_CLK setting");
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#if defined(APB4DIV_VAL)
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BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MAX_OFMCLK &&
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APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(8) &&
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(APB4DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB4_CLK setting");
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#endif
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#if defined(CONFIG_I3C_NPCX)
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BUILD_ASSERT(OFMCLK / (MCLKD_SL + 1) <= MHZ(50) &&
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OFMCLK / (MCLKD_SL + 1) >= MHZ(40),
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"Invalid MCLKD_SL setting");
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BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(20),
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"Invalid PDMA CLK setting");
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#endif
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static int npcx_clock_control_init(const struct device *dev)
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{
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struct cdcg_reg *const inst_cdcg = HAL_CDCG_INST(dev);
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const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;
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if (IS_ENABLED(CONFIG_CLOCK_CONTROL_NPCX_EXTERNAL_SRC)) {
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inst_cdcg->LFCGCTL2 |= BIT(NPCX_LFCGCTL2_XT_OSC_SL_EN);
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}
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/*
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* Resetting the OFMCLK (even to the same value) will make the clock
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* unstable for a little which can affect peripheral communication like
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* eSPI. Skip this if not needed.
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*/
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if (inst_cdcg->HFCGN != HFCGN_VAL || inst_cdcg->HFCGML != HFCGML_VAL
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|| inst_cdcg->HFCGMH != HFCGMH_VAL) {
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/*
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* Configure frequency multiplier M/N values according to
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* the requested OFMCLK (Unit:Hz).
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*/
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inst_cdcg->HFCGN = HFCGN_VAL;
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inst_cdcg->HFCGML = HFCGML_VAL;
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inst_cdcg->HFCGMH = HFCGMH_VAL;
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/* Load M and N values into the frequency multiplier */
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inst_cdcg->HFCGCTRL |= BIT(NPCX_HFCGCTRL_LOAD);
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/* Wait for stable */
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while (IS_BIT_SET(inst_cdcg->HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG)) {
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;
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}
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}
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/* Set all clock prescalers of core and peripherals. */
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inst_cdcg->HFCGP = VAL_HFCGP;
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inst_cdcg->HFCBCD = VAL_HFCBCD;
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inst_cdcg->HFCBCD1 = VAL_HFCBCD1;
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inst_cdcg->HFCBCD2 = VAL_HFCBCD2;
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#if defined(CONFIG_SOC_SERIES_NPCX4)
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inst_cdcg->HFCBCD3 = VAL_HFCBCD3;
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#endif
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/*
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* Power-down (turn off clock) the modules initially for better
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* power consumption.
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*/
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for (int i = 0; i < ARRAY_SIZE(pddwn_ctl_val); i++) {
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NPCX_PWDWN_CTL(pmc_base, i) = pddwn_ctl_val[i];
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}
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/* Turn off the clock of the eSPI module only if eSPI isn't required */
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if (!IS_ENABLED(CONFIG_ESPI)) {
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL6) |= BIT(7);
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}
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return 0;
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}
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const struct npcx_pcc_config pcc_config = {
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.base_cdcg = DT_INST_REG_ADDR_BY_NAME(0, cdcg),
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.base_pmc = DT_INST_REG_ADDR_BY_NAME(0, pmc),
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};
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DEVICE_DT_INST_DEFINE(0,
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npcx_clock_control_init,
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NULL,
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NULL, &pcc_config,
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PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&npcx_clock_control_api);
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